Cadence Design Systems, Inc announced that NextG-Com has completed its port of the ALPS520 LTE Layer 2 and 3 protocol to the Cadence Tensilica ConnX BSP3 processor core. This combined hardware/software solution can be used to speed the design of LTE modems for cellular phones, tablets and other end-user equipment.

Cadence Design Systems, Inc announced that QNX has ported its QNX Acoustics for Active Noise Control (ANC) software to the Cadence Tensilica HiFi Audio/Voice digital signal processing (DSP) core. The Tensilica HiFi Audio/Voice DSP from Cadence is available immediately. 

Cadence Design Systems has announced that a production proven host controller intellectual property (IP) for USB 3.0 has been added to the Cadence IP offering. The Cadence USB 3.0 xHCI host controller IP was originally developed by Fresco Logic, a global fabless semiconductor company that develops and markets advanced connectivity solutions.

Cadence Design Systems have announced that ON Semiconductor has adopted Virtuoso Layout Suite for Electrically Aware Design (EAD) for real-time electrical analysis of parasitic and electromigration impact on its custom physical design implementation flow. With Virtuoso Layout Suite EAD, ON Semiconductor circuit and layout designers will be able to significantly reduce design time and improve the energy efficiency of their designs by immediately s...

Cadence Design Systems Inc announced that its high-performance FastSPICE simulator, Spectre XPS (eXtensive Partitioning Simulator) now supports transistor-level mixed-signal design. Delivering up to 10X faster throughput versus previous advanced-SPICE solutions, Spectre XPS enables faster and more comprehensive simulation for large, complex designs including mixed-signal designs.

Cadence Design Systems Inc announced the signing of the first EDA (Electronic Design Automation) Technology Access Agreement with ARM Holdings plc that includes access to the ARM Cortex-A50 processor series, based on the ARMv8-A 64-bit architecture. This agreement also provides access to ARMv7 32-bit processor technology, ARM Mali GPUs (graphic processor units), System IP and ARM Artisan libraries. This collaboration further enables ARM and Caden...

Cadence Design Systems Inc announced that CSR plc selected the Cadence Palladium XP verification computing platform for system and early firmware validation of ARM-based automotive infotainment systems-on-chip (SoCs). Using Palladium Hybrid technology, CSR experienced a 200X speed-up for OS bringup, which shaved months off the development cycle. 

Cadence Design Systems, Inc announced immediate availability of DDR4 PHY IP (intellectual property) built on TSMC’s 16nm FinFET process. The combination of 16nm technology and Cadence’s innovative architecture helps customers realize the maximum performance of the DDR4 standard, which is specified to scale up to 3200Mbps, as compared to today’s maximum of 2133Mbps for both DDR3 and DDR4 technologies. This technology enables serv...

Cadence Design Systems has completed the acquisition of Jasper Design Automation. The completion of this transaction expands differentiation of Cadence’s System Development Suite, the industry’s first and broadest system design and verification platform. The combination of Jasper and Incisive Formal technologies and expertise will result in the most complete formal and semi-formal offerings in the industry.

An integrated solution to significantly cut down die-package interconnect planning time has been introduced by Cadence Design Systems. The solution, built on Cadence OrbitIO technology, reduces iterations between silicon and package design teams whilst also shortening the time to converge on the physical interface between the die and package up to 60%, all within the context of the full system.    

Cadence Design Systems has introduced what the company claims to be the industry’s first verification IP (VIP) supporting PCI Express (PCIe) 4.0 architecture. This VIP enables designers to quickly and thoroughly complete the functional verification for their system-on-chip (SoC) designs with less effort and greater assurance that the design will operate as expected.

Cadence Design Systems has announced availability of two intellectual property (IP) solutions for third-party designs on the 28nm FD-SOI process node that is accessible via the agreement between STMicroelectronics and Samsung. On this process node, the Cadence Denali DDR4 IP supports up to 2667Mb/s performance, enabling developers requiring high-memory bandwidth for applications such as servers, network switches and storage fabric to quickly take...

Cadence Design Systems has announced that an optimised port of Sonic Emotion’s Absolute 3D sound software is now available on the company's Tensilica HiFi Audio/Voice digital signal processing (DSP) family. The first time Absolute 3D sound software has been ported to a licensable IP DSP core, this brings the technology to a broad range of OEMs and end-equipment manufacturers.

Cadence Design Systems is to buy Jasper Design Automation. The combination of Cadence’s System Development Suite and Jasper’s multiple verification solutions built on the JasperGold platform will expand differentiation of Cadence’s system verification platform, and will be tightly integrated with Cadence’s common debug analysis, formal and semi-formal solutions, simulation, acceleration, emulation and prototyping platforms...

Cadence Design Systems has entered into a definitive agreement to acquire Jasper Design Automation, Inc., a provider of formal analysis solutions, for approximately $170m in cash. Jasper had approximately $24 million of cash, cash equivalents and short-term investments as of December 31, 2013.

Digital tools from Cadence Design Systems have received V1.0 DRM and SPICE certification for TSMC’s 16nm FinFET process, enabling joint customers to begin taping out FinFET-based designs using Cadence tools. Cadence’s digital, custom/analog and signoff tools have been co-optimized with TSMC’s 16nm FinFET process to enable higher performance, lower power consumption and smaller area for advanced designs.

Yamaha has used components of the Cadence Low-Power Solution to achieve a 50% reduction in leakage power in its latest chip for smartphones. Yamaha selected Cadence Encounter RTL Compiler, Cadence Encounter Conformal Low Power and Cadence Encounter Digital Implementation System.

Cadence Design Systems and JSC Mikron have announced today that Mikron has licensed Cadence Physical Verification System (PVS) and Cadence QRC Extraction to be used in Mikron’s basic 90nm IC design flow.

Featuring several enhancements, Cadence Design Systems has announced an expansion of its ARM-based design system verification solution in order to drive shorter time-to-market for mobile, networking and server applications. The system speeds system design and early software development for ARMCortex-A processor series based systems.

Cadence Design Systems has announced that GLOBALFOUNDRIES certified the Cadence PVS for custom/analog, digital and mixed-signal design physical signoff for 65nm to 14nm FinFET process technologies. The certification covers Cadence-qualified PVS rule decks for physical verification used in Cadence Virtuoso® Integrated Physical Verification System, Cadence Encounter Digital Implementation System and full-chip signoff.