Cadence Design Systems
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- http://www.cadence.com
- + 44.1344.869647
Cadence Design Systems Articles
Design tools complement 28nm Super Low Power process to achieve 2.0GHz performance
Cadence Design Systems and GLOBALFOUNDRIES have jointly announced the delivery of quad-core silicon built around the ARM Cortex-A17 processor, implemented using GLOBALFOUNDRIES’s 28nm Super Low Power (28nm-SLP) process with High-K Metal Gate (HKMG) technology. GLOBALFOUNDRIES utilised Cadence tools exclusively to achieve 2.0GHz processor performance at typical operating conditions, which matched pre-silicon design performance pred...
Automotive systems of the future at embedded world
As the automotive industry works towards autonomous vehicles, future cars are expected to be equipped with sensor clusters, more computing power, Car2X communication technology, Ethernet networks and HD displays. At embedded world, under the theme 'Building the car of the future today', Cadence will demonstrate its solutions for ADAS, Infotainment, ECU design, Ethernet and verification.
Verifier delivers up to 10 times productivity improvement
Cadence Design Systems has introduced the Perspec System Verifier platform for use-case scenario-based software-driven SoC verification. Using an intuitive graphical specification of system-level verification scenarios and a definition of the SoC topology and actions, this solution automates system-level coverage-driven test development using constraint-solving technology, delivering up to 10 times productivity improvement in SoC verification ver...
Sonics Adopts Cadence JasperGold Apps Formal Verification for On-Chip Network IP Development
Cadence Design Systems, Inc today announced that Sonics, Inc. has adopted Cadence JasperGold Apps in the formal verification methodology for its intellectual property (IP). Sonics’ on-chip network IP integrates multiple heterogeneous cores in a system-on-chip (SoC) using configurable interconnect fabric and multiple, on-chip communication protocols including the native PIF interface of Cadence Tensilica Xtensa DPUs. Sonics is initially depl...
Verification IP supports 25G Ethernet specification
Cadence Design Systems has launched Verification IP (VIP) that supports the new 25-Gigabit (25G) Ethernet specification. The 25G Ethernet specification extends the IEEE 802.3 standard to include operation at 25 Gb/s over copper cables and backplanes and increases server network throughput without using more interconnect lanes.
Characterisation solution delivers 20x performance improvement
With the increasing complexity of SoCs, and the industry shift towards intellectual property (IP) reuse and digital-on-top design flows for signoff with static analysis tools, Liberty representations are required for all blocks in the design including mixed-signal macros. To simplify this process, Cadence Design Systems has introduced the Virtuoso Liberate AMS characterisation solution which automates standard Liberty model creation for large mi...
Verification IP supports popular 3D memory standards
Cadence's Verification IP (VIP) supports all popular 3D memory standards, including Wide I/O 2, Hybrid Memory Cube (HMC), High Bandwidth Memory (HBM) and DDR4 3D Stacking (DDR4-3DS). The portfolio of memory VIP allows designers to accelerate the verification of memory interfaces and achieve earlier SoC verification closure for compute server applications, mobile devices, high-performance graphics and network applications.
Safety verification reduces ISO 26262 compliance preparation by 50%
Claimed to reduce the effort required by automotive designers to prepare for ISO 26262 compliance by up to 50%, Cadence Design Systems has introduced an automotive functional safety verification solution. The fault injection and safety verification technologies, which help automotive engineers automate ISO 26262 compliance for traceability, safety verification and tool confidence level, are an expansion to the company’s Incisive functional ...
Digital audio interface solution meets MIPI spec
The industry’s first MIPI SoundWireSM Controller Intellectual Property (IP) has been released by Cadence. SoundWire is a new digital audio interface specification from the MIPI Alliance that enables bi-directional digital communication with a focus on low complexity and low gate count, making it attractive to many mobile design applications.
Cadence and ARM Expand System-on-Chip Design Collaboration with New Multi-Year Technology Access Agreement
Cadence Design Systems, Inc. and ARM today announced the signing of a multi-year Technology Access Agreement. Expanding upon the successful EDA Technology Access Agreement signed in May 2014, this new agreement gives Cadence rights to access to existing and future ARM Cortex processors, ARM Mali GPUs, ARM CoreLink System IP, ARM Artisan physical IP, and ARM POP IP. This partnership enables ARM and Cadence to continue providing customers with adva...
Cadence Digital and Custom/Analog Tools Achieve TSMC Certification for 16FF+ Process
Cadence Design Systems, Inc announced that its digital and custom/analog tools have achieved V0.9 Design Rule Manual (DRM) and SPICE certification from TSMC for its 16FF+ process, enabling systems and semiconductor companies to take advantage of the 15 percent speed improvement with the same total power compared to 16nm FinFET, or 30 percent total power reduction at the same speed compared to 16nm FinFET. 16FF+ V1.0 certification is on track to b...
TSMC update enables development of IoT & wearable devices
To enable the rapid development of IoT and wearable devices, Cadence and ARM are updating 55ULP, 40ULP and 28ULP TSMC process technologies. Together, the companies will integrate ARM Cortex processors, ARM CoreLink system IP and ARM Artisan physical IP along with RF/analogue/mixed-signal IP and embedded flash in the Virtuoso-VDI Mixed-Signal Open Access integrated flow for theTSMC process technology.
TSMC selects Cadence library characterisation tool setting
Cadence has revealed that TSMC has adopted the company's solutions for 16nm FinFET library characterisation. Based on Cadence Virtuoso Liberate characterisation solution and Spectre circuit simulator, the library characterisation tool setting includes environment setup and sample templates for TSMC standard cells.
EMIR solution aims to create fastest path to design closure
A transistor-level EMIR solution, designated the Voltus-Fi Custom Power Integrity Solution, has been introduced by Cadence. Delivering foundry-certified, SPICE-level accuracy in power signoff, the solution aims to create the fastest path to design closure. Enabled by the company's Spectre Accelerated Parallel Simulator signoff SPICE simulation, the company claims that the solution provides best-in-class accuracy at the transistor level, thereby m...
Tool targets the acceleration of mainstream PCB design
Three additions to the Cadence OrCAD product line has been introduced, targeting the acceleration of the mainstream PCB design process and the boosting of productivity and efficiency. The OrCAD products include OrCAD Engineering Data Management (EDM), a comprehensive collaboration and management environment for OrCAD Capture; OrCAD Library Builder, a rapid automated part builder; and OrCAD Documentation Editor, an intelligent, automated PCB docum...
Prototyping tool speeds time-to-market
A prototyping tool which speeds time-to-market, has been introduced by Cadence. Protium is an expansion of the Cadence Palladium XP II suite. Built using Xilinx Virtex-7 2000T FPGAs, the prototyping tool provides automated memory compilation, external bulk memory support, and RTL name preservation throughout the flow, which minimises FPGA bring-up steps, thereby speeding up time-to-market.
Cut design flow parasitic extraction time in half
Following rigorous competitive evaluation, Ricoh implemented the Cadence Quantus QRC Extraction solution. Utilising it for all large-scale, complex digital designs and mixed signal power management ICs for their mobile products, this parasitic extraction solution enabled Ricoh to cut its design flow parasitic extraction time in half for SoC designs.
RC extraction tool accelerates design signoff
Delivering up to five times faster runtime for single and multi-corner extraction versus competing solutions, Cadence Design Systems has announced its next-generation tool for RC extraction. Quantus QRC Extraction solution accelerates design signoff and sets a new standard for performance with its massively parallel architecture.
Extraction solution certified for TSMC 16nm FinFET
Cadence Design Systems' Cadence Quantus QRC Extraction solution has been certified for TSMC 16nm FinFET. The solution successfully passed TSMC’s rigorous parasitic extraction certification requirements to achieve best-in-class accuracy against the foundry golden data for FinFET technology.
28mn design taped out using timing signoff tool
Allowing for the analysis of over 50M cells flat in the design, the Cadence Tempus Timing Signoff Solution has been used by Hitachi for its latest giga-scale design. Hitachi also utilised Tempus Timing Signoff Optimization (TSO), which resulted in a reduction of overall closure time to just 3 weeks, down from almost 2 months.