Cadence Design Systems plans to host its 10th CDNLive EMEA user conference from 27th to 29th April 2015, in Munich/Unterschleißheim. CDNLive EMEA offers the company users, developers and industry experts an opportunity to connect, share and inspire each other and discover new techniques and methodologies for realising innovative products.

Cadence Design Systems has announced that its digital and custom/analogue tools have achieved certification from TSMC for its most current version of 10nm FinFET Design Rule Manual (DRM) and SPICE models. The custom/analogue and digital implementation and signoff tools have been certified by TSMC on high-performance reference designs in order to provide customers with the fastest path to design closure on the 10nm FinFET process.

Cadence Design Systems and Accusonus have jointly announced that the Accusonus Focus-MDR and Focus-DNR speech enhancement software has been ported to and optimised for Cadence's Tensilica HiFi Audio/Voice DSPs. The Accusonus software provides the first integrated solution for reverberation and noise supression, suitable for challenging indoor acoustic environments.

Cadence Design Systems and ARM recently announced the signing of a broad IP interoperability agreement. This multiyear agreement provides reciprocal access to relevant IP portfolios from the Cadence IP Group and ARM.

Cadence and Intel have announced a 14nm library characterisation reference flow for customers of Intel Custom Foundry, continuing their collaboration on enabling digital and custom/analogue flows for the Intel 14nm platform. The library characterisation reference flow is centered on the Cadence Virtuoso Liberate Characterisation solution and Spectre Circuit Simulator and enables accurate 14nm logic libraries.

A physical implementation solution, which enables SoC developers to deliver designs with outstanding PPA (Power, Performance and Area), has been introduced by Cadence Design Systems. Driven by a massively parallel architecture with breakthrough optimisation technologies, the Innovus Implementation System provides typically 10-20% better PPA and five to ten times full-flow speedup and capacity gain at advanced 16/14/10nm FinFET processes and estab...

DTS’ Headphone:X immersive sound technology has been optimised for Cadence’s Tensilica HiFi Audio/Voice DSP family. This is an innovative sound technology designed to make movies, music and games more immersive by recreating an authentic, spatially accurate 3D audio home theatre experience over any set of headphones. 

Cadence has announced Stratus, the industry’s first high-level synthesis platform that can be utilised across an entire SoC design. This next-gen platform integrates Forte Cynthesizer and Cadence C-to-Silicon Compiler into one tool to deliver a tenfold productivity improvement, 20% better power, performance and area, and verification five times faster than a hand-written RTL flow.

  Epson is now using Cadence’s Tensilica Xtensa processor to power its GPS subsystem, extending the battery life of its wrist watch GPS running monitors from 14 hours to 30 hours.

At embedded world 2015, Cadence Design Systems will demonstrate its latest solutions for ADAS, infotainment, ECU design, automotive Ethernet, early software development and verification of embedded systems. In particular, the company will showcase its Tensilica infotainment solutions and Protium rapid prototyping platform, as well as functional safety and security verification, automotive Ethernet/ADAS, embedded system verification and debug...

After completing a competitive benchmark, MegaChips has selected Cadence’s Tensilica Xtensa processor for use within its frizz always-on sensor hub IC, designed for smartphones and IoT wearable devices. 

To speed up verification, silicon IP provider M31 Technology has utilised Cadence’s Verification IP (VIP) for PCIe 2.0. The VIP allows designers to perform verification tasks at more than twice the speed of a manual testbench. To simplify pre-silicon compliance verification, M31 Technology has also utilised Cadence’s TripleCheck IP Validator, which features a test suite, coverage model and verification plan. 

Cadence Design Systems and ARM have jointly announced the availability of a complete SoC development environment, supporting the ARM premium mobile IP suite that incorporates the latest ARM Cortex-A72 processor, ARM Mali-T880 GPU and ARM CoreLink CCI-500 Cache Coherent Interconnect solution.

To enhance the Cadence Tensilica Image Video Processing (IVP) DSP for use with the ARM Mali media IP suite, Cadence has licensed the ARM Frame Buffer Compression (AFBC) protocol. This is intended to provide a broad range of mobile users of ARM and Cadence media IP with significantly reduced system bandwidth and power requirements. In addition, the agreement also allows the Cadence Display Transmitter PHY to support the ARM Mali media IP suite to ...

Espressif Systems has selected the Cadence Tensilica Xtensa processor for use in its ESP8089 and ESP8266 WiFi chips, which are optimised for IoT applications. To achieve the best power, performance and area results, Espressif have customised the processor. The processor will be used as a DSP and control processor with a RTOS that runs Espressif’s WiFi and TCP/IP stacks and other application software. 

Aiming to enable product creation efficiency by increasing signoff-level PCB extraction accuracy, Cadence Design Systems has announced an expansion of its Sigrity technology portfolio. The Sigrity Parallel Computing 4-pack and the Sigrity System Explorer have been added to the range, as well as an updated power-aware system Signal Integrity (SI) feature and flexible purchasing options for PCB/IC Package design & analysis.

United Microelectronics (UMC) used Cadence Design Systems’ implementation and signoff tools to produce a silicon-ready 28nm ARM Cortex-A7 MPCore-based SoC, Cadence has announced. With the Cadence solution, UMC reduced the time to tapeout by 33% compared with its previous solution, and achieved performance of 1.7GHz.

Cadence Design Systems has announced the release of the Xtensa LX6 and the Xtensa 11, its 11th gen Tensilica Xtensa processors. The company’s latest gen processors allow users to create innovative custom processor instruction sets with up to 25% less processor logic power consumption and up to 75% better local memory area and power efficiency.

The Cadence Tensilica HiFi 4 audio/voice DSP IP core for SoC designs offers what Cadence hails as ‘the industry’s highest performance licensable DSP core for 32-bit audio/voice processing’. This 4th gen HiFi architecture enables emerging multi-channel object-based audio standards and doubles the performance of the HiFi 3 DSP, making it suitable for DSP intensive applications including digital TV, set-top box, Blu-ray Disc and au...

In order to deliver a complex 100G transport system design, Kansai-Chubu Net-Tech (KCN) utilised Cadence Design Systems' C-to-Silicon Compiler to shorten turnaround time by 40% compared to its traditional RTL process.