Cadence Design Systems has announced that Altair Semiconductor has adopted the Cadence Palladium XP platform for the verification and validation of its IoT SoC designs. Using the Palladium XP platform, Altair is able to conduct SoC hardware and software integration and validation three to four months ahead of silicon availability.

Cadence Design Systems has announced the Cadence Joules Register-Transfer Level (RTL) Power Solution. This RTL power analysis solution enables SoC design teams to analyse power consumption accurately during design exploration. Built on a multi-threaded architecture, the Joules RTL Power Solution delivers 20 times faster time-based RTL power analysis when compared to other methods.

Cadence Design Systems has announced that Realtek Semiconductor has utilised the Cadence Palladium XP platform to accelerate the successful development and verification of a recent SoC design. With the Palladium XP platform, Realtek achieved up to 250 times faster acceleration versus its previous methodology and was able to improve quality by executing system simulations six months before the silicon was available.

UltraSoC and Cadence Design Systems has announced that they have collaborated to provide support for the Cadence Tensilica Xtensa family of processors within UltraSoC's UltraDebug universal SoC debug solution.

  Cadence Design Systems has announced that Cyberon has optimised its CSpotter voice recognition software for the Cadence Tensilica Fusion and HiFi DSPs. CSpotter is a voice recognition engine that supports low-power always listening with keyword spotting.

Cadence Design Systems and Applied Materials have announced that they are collaborating on a development programme to optimise the Chemical-Mechanical Planarization (CMP) process through silicon characterisation and modelling for advanced-node designs at 14nm and below. The programme allows design teams to predict the impact of CMP on both functional yield and parametric yield, and for manufacturing teams to boost planarization performance, which...

Cadence Design Systems has announced that Cadence Innovus Implementation System has achieved v1.0 Design Rule Manual (DRM) certification from TSMC for its 16nm FinFET Plus (16FF+) process. The Innovus Implementation System successfully passed rigorous testing and has been validated by TSMC on high-performance reference designs in order to provide customers with a fast path to design closure.

Cadence Design Systems has announced that it is collaborating with TSMC on the development of an IoT IP subsystem demonstration platform for TSMC’s Ultra-Low Power (ULP) process. Targeting wearable, home automation, always-on and industrial control applications, this IP subsystem, with the support of the Cadence suite of digital and custom/analogue tools, provides the opportunity to simplify IoT designs and accelerate the time-to-market for...

Cadence Design Systems has announced the next-gen Cadence JasperGold formal verification platform. This formal verification solution integrates Cadence Incisive formal technology and JasperGold technology into a single platform that delivers up to 15 times performance improvement versus previous solutions. Moreover, as an integrated part of the Cadence System Development Suite, the JasperGold technology can help to reduce verification schedule by...

Cadence Design Systems has announced that its implementation and signoff tools have achieved certification on the Intel 14nm process for customers of Intel Custom Foundry, which utilised a PowerVR Series6 GPU from Imagination Technologies as part of the certification process. The tool certification and enablement provides Intel Custom Foundry customers with a complete and integrated SoC design flow.

To address the productivity challenges faced by RTL designers, Cadence Design Systems has released the Cadence Genus synthesis solution, its next-gen RTL synthesis and physical synthesis engine.

Steve Rogerson reports from Cadence’s CDN Live user conference in Munich.

Cadence Design Systems has announced that it is collaborating with Imagination Technologies to enhance RTL designer productivity and enable faster design convergence on Imagination graphics cores and other Imagination IP using the Cadence Genus synthesis solution. On the PowerVR GE7800 GPU, the Genus synthesis solution achieved a five times improvement in turnaround time versus the previous Cadence synthesis solution with no impact on Power, Perf...

Cadence Design Systems has unveiled its Allegro 16.6 portfolio, which features several product and technology introductions. Driven by increasing demands to provide a more predictable and shorter design cycle, the Allegro 16.6 portfolio includes more capabilities that accelerate routing and tuning for high-speed interfaces such as DDR3 and DDR4.

The USB 3.0 host IP solution for TSMC’s 16nm FinFET Plus (16FF+) process is one of the first to pass USB-IF compliance testing and receive USB-IF certification, maker Cadence has announced. The complete controller and PHY integrated solution is pre-verified, which enables designers to mitigate project risk and reduce SoC integration and verification time.

Cadence Design Systems and Conexant Systems have announced that Conexant’s AudioSmart software has been optimised for the Cadence Tensilica HiFi DSP family. The software provides clear voice quality, eliminates noise from the microphone input signal during VoIP calls, and dramatically improves Automatic Speech Recognition system performance. The result is a superior audio experience for the end user, with outstanding listening performance a...

A debugging solution which reduces the time to identify bugs in a design by up to 50% compared to traditional signal- or transaction-level debug methods has been released by Cadence Design Systems. In addition to the Indago debug platform, the company has also introduced three debugging apps that plug into the platform and can be used with other verification tools to provide a single integrated and synchronised debug solution for testbench, verif...

Suitable for applications requiring merged controller plus DSP computation, ultra-low energy and a small footprint, the Tensilica Fusion DSP has been released by Cadence Design Systems. Based on the Xtensa customisable processor, the device can be designed into SoCs for wearable activity monitoring, indoor navigation, context-aware sensor fusion, secure local wireless connectivity, face trigger, voice trigger and voice recognition.

Cadence Design Systems has announced five OrCAD products and three key feature updates as it celebrates 30 years of continued OrCAD design and innovation. The expanded OrCAD portfolio enables greater product creation efficiency by delivering additional high-speed design capabilities that address productivity and time-to-market challenges.

Cadence Design Systems has announced that FreeRTOS (a popular, scalable, easy-to-use real-time kernel designed specifically for small, low-power embedded systems) is now available for Cadence Tensilica processors and DSPs. According to a 2013 market share study from UBM Tech, FreeRTOS had been selected for 13% of embedded projects that utilise an embedded OS and is a very popular option for MCUs as well as smaller 32-bit processor cores.