Cadence Design System has announced that dbx-tv’s Total Technology audio enhancement suite is now available on the Cadence Tensilica HiFi audio/voice DSP family. The Total Technology suite offers several technologies working together, which result in optimal audio quality that creates the best sound available from the TV’s built-in high-performance speakers.

Cadence Design Systems has collaborated with Lumerical Solutions and PhoeniX to jointly develop an integrated Electronic/Photonic Design Automation (EPDA) environment for Photonic ICs (PICs). Built around the Cadence Virtuoso custom design platform, the EPDA environment enables schematic or layout-driven design flows for photonic and electronic circuits, photonic component parameter extraction and model generation, photonic circuit simulation and...

The Dynamic Speaker Management (DSM) software from Maxim Integrated has been ported and optimised to efficiently run on Cadence Tensilica HiFi Audio/Voice DSPs. Designers are typically faced with inherent problems, including weak sound and lack of bass response within micro speakers. In addition, they can easily break and produce distorted sound. Maxim’s technology balances bigger sound and better sound quality with lower power and improved...

A collaboration has been announced between Cadence Design Systems and Spreadtrum to develop a virtual reference design kit specific to Spreadtrum’s SC9830A quad-core system-on-chip (SoC) platform requirements.

Cadence Design Systems has announced the delivery of the new Virtuoso Advanced-Node Platform that is enabled for all advanced 10nm FinFET designs. This next generation custom design platform delivers up to 5X improvement in designer productivity and also provides initial support for emerging 7nm technologies.

Cadence Design Systems and Accusonus have announced that the Accusonus Focus-MDR and Focus-DNR speech enhancement software has been optimised for Cadence Tensilica HiFi Audio/Voice digital signal processors (DSPs). Accusonus was able to achieve a 60% reduction in computational cost as measured in megacycles per second (MCPS) without any loss of quality.

Cadence Design Systems has unveiled the Cadence Palladium Z1 enterprise emulation platform, the industry’s first datacenter-class emulation system, delivering up to five times greater emulation throughput than the previous generation, with an average two and a half times greater workload efficiency than the closest competitor.

Cadence Design Systems and Morpho has announced that Morpho’s MovieSolid and Morpho Video WDR are now available on the Cadence Tensilica Vision P5 digital signal processor (DSP). Ported by vision industry experts at Morpho, these products make it much easier for designers to offer applications with advanced stabilisation and image-correction capabilities with lower power consumption. MovieSolid is an embedded software programme for stabilis...

Cadence Design Systems has announced a reference system jointly developed with ARM that is targeted at Internet of Things (IoT) systems. This is the first product following the strategic IP Interoperability Agreement (IPIA) signed by Cadence and ARM that allows the companies reciprocal access to relevant IP portfolios.

The verification IP (VIP) for the ARM AMBA 5 Advanced High-Performance Bus 5 (AHB5) specification has been announced by Cadence Design Systems. The announcement covers two new VIP titles in Cadence’s portfolio including simulation VIP and assertion-based VIP.

It has been announced that the Digital and Signoff tools from Cadence Design Systems are now enabled for the current version of the GLOBALFOUNDRIES 22FDX platform reference flow.

Cadence Design Systems has announced that it now offers the industry’s first IP subsystem with pre-verified components including a single-chip port controller IP that integrates USB Type-C, USB Power Delivery and DisplayPort Alternate Mode (Alt Mode). This design IP enables the development of single-chip solutions for combining video, audio, USB and up to 100W of power on a single external connector.

Cadence has announced the Cadence Memory Model for the LPDDR5 standard. This Verification IP (VIP) product enables engineers to verify that SoC designs are compliant with the JEDEC interface standard, and that they can operate correctly in a system with the actual memory components. Validation of designs using the LPDDR5 memory model reduces the risk of mistakes, rework and delayed production, leading to faster production ramp-up and higher produ...

Cadence Design Systems has announced the Cadence Tensilica Vision P5 DSP, its flagship high-performance vision/imaging DSP core. This imaging and vision DSP core offers up to a 13-fold performance boost, with an average of five times less energy usage on vision tasks compared to the previous generation IVP-EP imaging and video DSP.

Cadence Design Systems has announced a broad IP portfolio for TSMC’s 10nm FinFET (N10) process. Cadence has already secured multiple design wins with this portfolio and is actively engaged with customers as adoption of TSMC’s leading-edge process grows. The initial deliveries of Cadence IP for the N10 process demonstrate a 20% power reduction and 50% area reduction compared to TSMC’s 16nm process technology and are suitable for ...

Cadence Design Systems has announced that its Cadence Innovus implementation system has achieved V0.9 certification for TSMC’s 10nm FinFET process and is currently on track to complete V1.0 in Q4 2015. The Innovus implementation system is a next-gen physical implementation tool that incorporates integrated signoff engines that have been validated by TSMC on high-performance reference designs, providing customers with a fast path to implemen...

Cadence Design Systems has announced that its digital, custom/analogue and signoff tools have achieved certification from TSMC for V0.9 of its 10nm process and are currently on track to achieve V1.0 completion by Q4 2015. The certification enables system and semiconductor companies to deliver advanced-node designs to market faster for mobile phones, tablets, application processors and high-end servers.

Cadence Design Systems has announced that its Allegro System-in-Package (SiP) and Physical Verification System (PVS) implementation technologies have been enabled for TSMC’s Integrated Fan-Out (InFO) packaging technology. By providing an integrated solution that automates the Design-Rule Checking (DRC) flow, the Allegro SiP design tools and PVS enable TSMC customers to shorten the InFO design and verification cycle.

Cadence Design Systems, Mentor Graphics and Breker Verification Systems have announced that they have collaborated on a technology contribution to the Accellera Portable Stimulus Working Group. The contribution leverages the combined experience of the three companies in providing portable test and stimulus solutions, and is intended to assist the Accellera Portable Stimulus Working Group in defining a SoC verification standard that offers both ve...

Cadence Design Systems has named A-ZTech, a leading provider of engineering solutions for electronic design automation (EDA) as well as computer aided engineering (CAE), design, testing and production, as a value added reseller in Turkey. A-Ztech will cover the complete Cadence product portfolio including IP and training.