A collaboration between Amkor Technology and Cadence Design Systems has been extended in order to streamline semiconductor package verification with the joint development of a package assembly design kit (PADK) for Amkor’s SLIM and SWIFT advanced fan-out package technologies.

Cadence Design Systems has announced that it has completed the acquisition of Rocketick Technologies, an Israel-based pioneer and leading provider of multicore parallel simulation. The completion of this transaction strengthens Cadence’s System Design Enablement strategy by delivering ultra-high-performance simulation to accelerate the development of complete systems with the end-product in mind.

The Cadence Innovus Implementation System from Cadence Design Systems has been adopted by Toshiba Corporation for its memory controller’s production design project. The tool enabled Toshiba to achieve an optimal target performance while creating a 16% smaller place and route (P&R) area for random logic with 25% lower power consumption when compared with its previous solution.

Cadence Design Systems has announced that it has entered into a definitive agreement to acquire Rocketick Technologies. Rocketick’s technology accelerates Cadence Incisive Enterprise Simulator to provide up to six times more speed-up for register-transfer-level (RTL), up to ten times more speed-up for gate-level functional and up thirty times more speed-up for gate-level DFT simulations using standard x86-based servers.

Cadence Design Systems and the University of Oxford has announced a move to foster the advancement of formal verification innovation with the appointment of Dr. Ziyad Hanna, Vice President of R&D, Cadence, as a visiting professor in Oxford’s Department of Computer Science for the next three years.

Cadence Design Systems has announced the delivery of the next-gen Virtuoso platform which offers designers an average of 10x performance and capacity improvement across the platform. The platform includes new technologies within the Cadence Virtuoso Analog Design Environment (ADE) and enhancements to the Cadence Virtuoso Layout Suite to address requirements for automotive safety, medical device and IoT applications.

Cadence Design Systems has announced that Ethertronics, a leader in ultra-high performance smart antenna system solutions, used Cadence Conformal ECO Designer to completely redesign the digital interface section of a complex RF/mixed-signal design by reusing transistors in the base layers, enabling the redesign in a metal only change.

A complete suite of digital and sign-off tools from Cadence Design Systems has achieved certification for Samsung Foundry’s Process Design Kit (PDK) and foundation library for the 14LPP process.

Jointly sponsored by Cadence Design Systems, Coventor, X-FAB and Reutlingen University, a MEMS Design Contest is being launched at DATE 2016. The objective of this contest is to encourage greater ingenuity with regard to the integration of MEMS devices and mixed-signal CMOS blocks.

Cadence Design Systems and Realtek Semiconductor has announced that Realtek has licensed the Cadence Tensilica Fusion Digital Signal Processor (DSP) to support ultra-low-power functionalities in its Context Hub chip. Realtek collaborated with Cadence software partners CyweeMotion and Cyberon to integrate their sensor fusion and voice-trigger always-on functions (respectively) to Realtek’s RTS3110/RTS3111 chip.

Cadence Design Systems has announced that Silicon Labs used a Cadence mixed-signal low-power flow to reduce overall design time, significantly speeding time to market. Silicon Labs adopted the flow for its Blue Gecko family of wireless SoC devices that provide ultra-low-power Bluetooth Smart connectivity for IoT applications. 

An audio software framework that provides OEMs and application developers faster time to market when integrating Tensilica HiFi DSP-based systems on chip (SoCs) into their products has been introduced by Cadence. The announcement also includes the availability of the first hardware integration into the Android Studio development platform.

Cadence Design Systems has announced that OrCAD Capture now provides export capability for Intel Schematic Connectivity Format (ISCF), targeted at automating Intel-based design reviews. ISCF was developed by Intel to streamline the collaboration process with its customers. Intel worked with Cadence to develop a direct ISCF generation capability in OrCAD Capture to make this collaboration process simpler and more efficient.

Cadence Design Systems has announced that the Cadence Innovus Implementation System has been qualified for Samsung Foundry’s latest 10nm process. The Innovus Implementation System is a next-gen physical implementation tool with integrated signoff engines that have been validated for Samsung designs, providing customers with the fastest path to implementation and closure and optimal Power, Performance and Area (PPA).

Cadence Design Systems has delivered a complete digital and sign-off reference flow for Imagination Technologies’ PowerVR Series7 graphics processing units (GPUs). 

Cadence Design Systems' Modus Test Solution enables design engineers to achieve up to a three times reduction in test time, thereby reducing production test cost and increasing silicon profit margins. This next-gen solution incorporates patent-pending, physically aware 2D Elastic Compression architecture that enables compression ratios beyond 400 times without impacting design size or routing.

Cadence Design Systems has announced the availability of the Sigrity 2016 technology portfolio, which improves product creation time with an enhanced PCB design and analysis methodology that is suited for multi-gigabit interfaces.

Cadence Design Systems has announced that its audio core for SoC designs has been approved for use with the Dolby MS12 Multistream Decoder, an all-in-one audio solution for TVs with universal decoding, that supports Dolby Digital Plus, Dolby, Digita, HE-AAC decoding, Dolby Audio Processing (DAP) post-processing, system sound mixing and speaker tuning.

Arthur Schaldenbrand, Cadence Design Systems, discusses some of the power design challenges that have emerged over recent years as well as some promising new technologies to address them.

DSP Concepts’ graphical audio development tool, Audio Weaver, has been optimised for Cadence Tensilica HiFi audio/Voice DSPs. This technology from DSP Concepts is an innovative design environment for developing optimised embedded audio software. Development teams can create applications that realise their desired sound quality up to 10 times faster than traditional development approaches by allowing developers to work in parallel at differe...