Cadence Design Systems announced immediate availability of the Dolby Laboratories' AC-4 Decoder supporting next-gen audio and video entertainment services, including ATSC 3.0 broadcasting and internet streaming on Cadence Tensilica HiFi DSPs. HiFi DSPs are the first processors for SoC designs approved for using the Dolby AC-4 Decoder. The Dolby AC-4 Decoder is critical to next-generation TV and set-top box (STB) designs.

Cadence Design Systems announced immediate availability of the next-generation MPEG-H Audio decoder based on Cadence Tensilica HiFi DSPs. MPEG-H Audio is a future broadcast standard and is expected to be one of the key audio technologies adopted worldwide for TVs. Through close collaboration with Fraunhofer, one of the developers of the open ISO MPEG-H Audio standard, Cadence is first to market with an implementation for a licensable DSP.

Cadence Design Systems has announced a broad portfolio of Cadence interface and Denali memory IP solutions for automotive applications supporting TSMC’s 16nm FinFET Compact (16FFC) process. By offering a wide array of IP using TSMC’s 16FFC process, Cadence is enabling automotive customers to accelerate time to market while gaining the benefits of TSMC’s most advanced process technology used in automotive applications.

The availability of a Cadence Rapid Adoption Kit (RAK) for the ARM Cortex-R52 CPU, which targets complex embedded designs for safety applications in markets including automotive, medical and industrial has been announced by Cadence Design Systems.

Cadence Design Systems announced immediate availability of the next-gen MPEG-H Audio decoder based on Cadence Tensilica HiFi DSPs. MPEG-H Audio is a future broadcast standard and is expected to be one of the key audio technologies adopted worldwide for new TVs. Through close collaboration with Fraunhofer, one of the developers of the open ISO MPEG-H Audio standard, Cadence is first to market with an implementation for a licensable DSP.

Cadence Design Systems announced immediate availability of the Dolby Laboratories' AC-4 Decoder supporting next-gen audio and video entertainment services, including ATSC 3.0 broadcasting and internet streaming on Cadence Tensilica HiFi DSPs. HiFi DSPs are the first processors for SoC designs approved for using the Dolby AC-4 Decoder. The Dolby AC-4 Decoder is critical to next-generation TV and set-top box (STB) designs.

Irida Labs’ IRIS-EnLight and IRIS-NoiseSweeper technologies are now available on the Cadence Tensilica Vision family of DSPs. Developed by vision industry experts at Irida Labs, these new technologies enable mobile, automotive, home electronics and wearables designers to achieve improvements in performance while using less power compared with common CPU and GPU implementations.

Cadence Design Systems have delivered what the company claims to be the industry’s first Design and Verification IP for MIPI SoundWire v1.1 and demonstrated interoperability of MIPI SoundWire solutions in collaboration with Realtek. SoundWire is a digital audio interface specification that can replace legacy audio interfaces, reducing the cost of supporting high quality audio through reduced pin count, ease of integration and low gate ...

As Cadence’s Bob Salem explains, advances in mobile and Internet of Things (IoT) applications are challenging chip designers to deliver increasing performance and longer battery life.

Cadence Design Systems has announced the availability of the new Cadence Tensilica Fusion G3 DSP, a multi-purpose, high-performance DSP for compute-intensive SoC designs. The Tensilica Fusion G3 DSP is exceptionally easy to programme and suited for use in automotive, consumer, IoT and industrial applications that combine intensive audio, imaging, communications, radar and embedded DSP computation.

The implementation and signoff tools of Cadence Design Systems have achieved certification on the Intel 3rd gen 10nm tri-gate process for customers of Intel Custom Foundry. Intel Custom Foundry utilised a PowerVR GT7200 graphics processing unit (GPU) from Imagination Technologies as part of the certification process.

A team at Cadence Design Systems take a closer look at the new open standards being developed to improve the reliability and redundancy of automotive Ethernet. Ethernet is the key technology to enable advanced driver assistance systems (ADAS) and autonomous driving, owing to its low cost, low weight, high data rate and non-proprietary nature. 

Cadence Design Systems has announced the launch of PSpice.com, http://www.pspice.com/ a new user-community web portal that lets designers, partners and students access materials related to PSpice analog and mixed-signal simulation and analysis in one central location.

Cadence Design Systems has announced a collaboration with Semiconductor Manufacturing International Corporation (SMIC) on the delivery of a 28nm design reference flow that incorporates a full suite of Cadence digital products for low-power design. This reference flow is a 28nm low-power register-transfer level (RTL) to signoff flow based on the IEEE 1801 low power design and verification standard.

Cadence Design Systems has announced the industry’s first complete hosted end-to-end solution to enable designers to accelerate their custom SoC and IoT design process using ARM Cortex-M processors. This offering accelerates mixed-signal SoC design for IoT, incorporating the ARM IoT Subsystem for Cortex-M processors and Cadence’s interface IP and unified mixed-signal implementation solution, now optimised specifically for Cortex-M cor...

Cadence Design Systems has announced that Hitachi has adopted a Cadence Analog Mixed-Signal (AMS) model-based methodology and tools to shorten the verification cycle for one of its largest mixed-signal design projects. By upgrading its previous transistor-level methodology to a model-based methodology, Hitachi successfully accelerated mixed-signal verification for this project by 160X and reduced full-chip simulation time to 30 minutes.

Cadence Design Systems has announced that STMicroelectronics has qualified and actively deployed the next-gen Cadence Virtuoso platform for its SmartPower technologies. The latest Virtuoso platform successfully enabled ST design engineers to improve custom routing quality and performance and significantly reduce block-planning and pin-optimisation time using special pin groups and guide constraints.

Cadence Design Systems has announced the availability of a Rapid Adoption Kit (RAK) based on the ARM internal flow used for the design of the ARM Cortex-A73 CPU and the ARM Mali-G71 GPU that is geared toward enhancing VR and AR experiences on 2017 flagship mobile devices. During this process, Cadence and ARM also collaborated to develop a 10nm methodology using Cadence digital implementation and signoff tools.

Following an extensive evaluation process, Cypress Semiconductor has selected the full Cadence RTL-to-signoff digital design flow and complete Spectre circuit simulation platform for all of its 40nm automotive chip designs. The evaluation process gave Cypress the opportunity to dramatically improve its turnaround time and productivity with the Cadence solution when compared with its previous flow.

Faraday Technology, a fabless ASIC/SoC and IP provider, has used Cadence OrbitIO interconnect designer and Cadence SiP Layout to reduce their packaging design time by 60% compared to their previous methodology.