Cadence Design Systems has announced its collaboration with CommSolid, the cellular Internet of Things (IoT) company, to address the fast growing cellular IoT market with new baseband IP tailored for low power cellular communication compliant with 3GPP’s NarrowBand IoT (NB-IoT) communications standard.

  Cadence Design Systems announced that Cavium has now deployed the Cadence Palladium Z1 enterprise emulation platform to work toward increasing verification throughput for complex designs. After conducting an extensive evaluation, Cavium decided to deploy the Palladium Z1 platform for production use.

The availability of the Sigrity 2017 technology portfolio, which introduces several key features specifically designed to speed up PCB power and signal integrity signoff, has been announced by Cadence Design Systems.

AltaSens has adopted the Cadence Design Systems Modus Test Solution for its mixed-signal next-generation image sensors. By using the Modus Test Solution in conjunction with other Cadence digital and verification tools on a 90nm process technology, AltaSens has met its aggressive test coverage goals while saving several weeks on design convergence.

The availability of Cadence's Cadence Verification IP (VIP) for Bluetooth 5 has been announced, which it claims to be the industry’s first VIP for the latest version of Bluetooth technology. Bluetooth 5 increases data broadcasting capacity by 800%, quadruples the range and doubles the connection speed of low-energy devices to deliver seamless, short-range mobile connectivity.

  It has been announced that Almalence has collaborated with Cadence to port their Video SuperSensor video image quality improvement software to the Cadence Tensilica Vision DSP. 

Cadence Design Systems has announced that Fortemedia has licensed the Cadence Tensilica Fusion F1 DSP as the engine of its next-gen smart microphone processor to support always-on voice trigger and sensor fusion capabilities for voice wake-up in mobile, Internet of Things (IoT) and consumer applications.

Cadence Design Systems and Retune DSP have announced that Retune DSP’s multi-microphone beamforming and echo cancellation technology has been ported and optimised to Cadence Tensilica HiFi DSPs for Audio/Voice/Speech. Optimised DSPs such as the Tensilica HiFi DSP that are efficient, low power and high performance are well suited for voice-processing applications.

In order to enable the world’s first TVs featuring Dolby Atmos technology based on the Dolby MS12 v2.0 Multistream Decoder, Cadence Design Systems has collaborated with Dolby Laboratories. The MS12 v2.0 Multistream Decoder is an early adopter release for the Cadence Tensilica HiFi DSP core for System-on-Chip (SoC) designs. 

Cadence Design Systems has announced that Sentons licensed the Cadence Tensilica ConnX BB32EP DSP for an ultrasound technology that is changing the human interface landscape for mobile and touch-enabled devices. Sentons selected the ConnX DSP for its complex signal processing performance in a low-power envelope for mobile applications. 

Cadence Design Systems has announced that its OrCAD Capture has been enhanced to include XJTAG DFT Assistant, an easy-to-use interface that significantly increases the Design For Test (DFT) and debug capabilities of the schematic capture and PCB design system.

Designers can now efficiently create safety-critical system-on-chip (SoC) designs using high-performance ARM processors using the Cadence Modus Test Solution which supports the ARM Memory Built-In Self Test (MBIST) interface. To demonstrate the success of the collaboration, Cadence and ARM have completed silicon validation using an ARM Cortex-A73 processor in conjunction with the Modus Test Solution’s automatic test pattern generation (ATPG...

Cadence Design Systems has announced it has partnered with MathWorks to streamline system-level design and circuit-level implementation for mixed-signal internet of things (IoT) and automotive applications.

Cadence Design Systems, Coventor, X-FAB and Reutlingen University have teamed up to launch the MEMS design contest to encourage the development of innovative MEMS and mixed-signal designs. The first-prize winner will receive a $5000 cash award, have their design manufactured at X-FAB’s wafer production facilities and get a free one-year license of Coventor’s MEMS design software.

Cadence Design Systems announced the availability of a Cadence Rapid Adoption Kit (RAK) for the new ARM Cortex-M23 and Cortex-M33 processors targeted for the development of secure IoT applications. The Cadence RAK consists of a complete digital implementation and signoff flow that designers can utilise to create low-power Cortex-M23 and Cortex-M33 devices quickly and efficiently, thereby enabling early silicon delivery.

It has been announced by Cadence Design Systems that its complete suite of digital and signoff tools has been certified for Samsung Electronics’ Process Design Kit (PDK) and Foundation Library on Samsung’s 2nd gen of 10nm LPP (Low Power Plus) process. Samsung also validated the Cadence reference flow using a quad-core design with the ARM Cortex-A53 processor on the 10LPP process.

Cadence Design Systems announced the release of 10 new VIP solutions that allow engineers to quickly verify that designs meet specifications for the latest standard protocols. This extension of Cadence’s leading VIP portfolio supports growth in high-bandwidth applications including video on demand, cloud computing, big data and high-resolution video used in the automotive, mobile, enterprise networking and consumer industries.

Cadence Design Systems announced that it has received four TSMC Partner of the Year awards at this year’s TSMC Open Innovation Platform (OIP) Ecosystem Forum. Cadence was presented with awards for the joint delivery of the 7nm mobile design platform, the 7nm HPC design platform, the Integrated Fan-Out (InFO) design solution and its analog/mixed-signal IP.

Cadence Design Systems announced general availability of the 12th gen Tensilica Xtensa base processor architecture. The Xtensa LX7 architecture makes new technologies available for customisation by Xtensa customers and increases floating-point choices from 2 to 64 FLOPS/cycle, meeting the growing need for precision and portability in today’s demanding DSP (digital signal processing) applications.

Cadence Design Systems announced several important deliveries in its collaboration with TSMC to advance 7nm FinFET designs for mobile and high-performance computing (HPC) platforms. As a result of the joint work, Cadence digital, signoff and custom/analog tools have achieved certification for the latest Design Rule Manual (DRM) and SPICE for the TSMC 7nm process. In addition, a new process design kit (PDK) enabling customers to achieve optimal po...