A virtual emulation technology that accelerates software bring-up in pre-silicon verification versus RTL simulation has been announced by Cadence Design Systems. The VirtualBridge Adapter allows software engineers to start their pre-silicon verification tasks with the Cadence Palladium Z1 Enterprise Emulation Platform up to three months earlier, complementing their traditional in-circuit emulation use model. The VirtualBridge Adapter is...

  A formal, streamlined and automated co-design and verification flow between the Cadence Virtuoso platform and Allegro and Sigrity technologies has been announced by Cadence Design Systems, the Cadence Virtuoso System Design Platform. This higher level of integration enables engineers to design concurrently across the chip, package and board.

The custom/analogue tools and full-flow digital and signoff tools from Cadence Design Systems have achieved certification for the process design kit (PDK) and foundation library for the Samsung Electronics’ 28nm fully depleted silicon-on-insulator (FDS), also known as FD-SOI, process technology.

Cadence Design Systems has announced that its digital, signoff and custom/analogue tools are enabled on Samsung Electronics’ 7LPP and 8LPP process technologies. The 7LPP and 8LPP process technologies continue to deliver power, performance and area optimisations with additional scaling benefits over previous generations of advanced FinFET nodes, and customers can begin working on early designs using these next-gen technologies.

Cadence Design Systems has announced the expansion of its JasperGold Formal Verification Platform with the introduction of the JasperGold Superlint and Clock Domain Crossing (CDC) Apps, advanced formal-based technologies that address register-transfer level (RTL) signoff requirements. The Superlint and CDC Apps bring the power of JasperGold formal technology to the RTL designer’s desktop.

Through a new integration between the Cadence Virtuoso Analog Design Environment (ADE) Product Suite and MATLAB, Cadence Design Systems has expanded its partnership with MathWorks. This enables customers to accelerate processing of large data sets when verifying custom, RF and mixed-signal designs. With this integration, designers can take advantage of existing MATLAB scripts and seamlessly share data between the Virtuoso and MATLAB platforms, al...

Cadence Design Systems has unveiled the Cadence Tensilica Vision C5 DSP, which it claims to be the industry’s first standalone, self-contained neural network DSP IP core optimised for vision, radar/lidar and fused-sensor applications with high-availability neural network computational needs. Targeted for the automotive, surveillance, drone and mobile/wearable markets, the Vision C5 DSP offers 1TMAC/sec computational capacity to run all neur...

In order to deliver multimedia System-on-Chip (SoC) designs to market faster, Amlogic has adopted Cadence Design Systems' new Cadence Protium S1 FPGA based prototyping platform. Using the Protium S1 platform, Amlogic accelerated its hardware/software (HW/SW) integration process, resulting in a time savings of two months compared to its previous traditional HW/SW integration method. 

  Cadence Design Systems has announced that the Cadence Tensilica Vision P-Series DSPs are the first imaging/vision DSPs to pass Khronos Group’s conformance tests for the OpenVX 1.1 specification. Application developers can now take advantage of Tensilica Vision P5/P6 functionality without detailed knowledge of the hardware architecture and still achieve high performance.

A massively parallel, cloud-ready physical verification signoff solution has been announced by Cadence Design Systems. The Pegasus Verification System enables engineers to deliver advanced-node ICs to market faster. The new solution is part of the full-flow Cadence digital design and signoff suite and provides up to ten times faster Design Rule Check (DRC) performance on hundreds of CPUs while also reducing turnaround time from days to ...

Cadence Design Systems has announced the release of the Virtuoso Advanced-Node Platform supporting advanced 7nm designs. Through collaboration with early 7nm FinFET customers, Cadence has expanded the Virtuoso custom design platform with innovative capabilities to manage design complexity and process effects introduced with this advanced-node process.

Cadence Design Systems has announced that Juniper Networks achieved first-pass silicon success for its largest System-on-Chip (SoC) design with hundreds of millions of instances on the latest FinFET process using the Cadence Voltus IC Power Integrity Solution. With the Cadence solution in place, Juniper yielded faster turnaround times and improved signoff accuracy when compared with its previous solution.

This whitepaper, the second in a series of DO-254-related whitepapers, will explore software tools as they relate to meeting the DO-254 Design Assurance Guidance for Airborne Electronic Hardware specifications, and what steps must be performed in order to use your typical design automation tools such as simulation, synthesis, etc.

This whitepaper, the first in a series of DO-254-related whitepapers, will explore the high level concepts and activities within the DO-254 Design Assurance Guidance for Airborne Electronic Hardware specification, why they exist, and what they mean.

  New optimisation capabilities have been announced within Cadence Design Systems' holistic, integrated design flow for TSMC’s advanced wafer-level Integrated Fan-Out (InFO) packaging technology. The integrated flow provides design and analysis capabilities and modeling of cross-die interactions for mobile and IoT applications. 

At embedded world 2017, Cadence Design Systems will showcase its latest Tensilica DSPs and design tools targeted for automotive applications. The demonstrations will take place in Hall 4/4-116 at the Exhibition Centre in Nuremberg, Germany from March 14th-16th 2017, where the theme of the event is 'Automotive Electronics Redefined.' The Cadence automotive-themed demonstrations will highlight the following:

Cadence Design Systems has announced the Cadence Litho Physical Analyser (LPA) Production Lithography Unified Solution (PLUS) developed in partnership with ASML, which seamlessly provides foundry-enabled lithography simulation capabilities during chip design implementation and signoff. Cadence LPA PLUS enables engineers to detect lithography hotspots during design implementation and physical signoff and automatically fix them in Cadence design pl...

Cadence Design Systems has announced what it claims to be the industry’s first production-ready third generation simulator, the Xcelium Parallel Simulator. It is based on multi-core parallel computing technology, enabling Systems-on-Chip (SoCs) to get to market faster. On average, customers can achieve two times improved single-core performance and more than five times improved multi-core performance versus previous generation Cadence simul...

Cadence Design Systems has announced the new Protium S1 FPGA-based prototyping platform, which incorporates implementation algorithms to boost engineering productivity. The Protium S1 platform provides front-end congruency with the Cadence Palladium Z1 Enterprise Emulation Platform, thereby delivering 80% faster design bring-up on average when compared to typical FPGA prototyping approaches.

Cadence Design Systems has announced that its Cadence Tensilica Fusion F1 DSP is part of the latest Methods2Business (M2B) WiFi HaLow MAC IP offering. The licensable IP targets SoCs designed for battery-powered sensor nodes used in smart home, smart city and industrial applications.