GÖPEL packages offers integration for ATE

JTAG/Boundary-Scan integration increases test coverage, improves diagnostics, and enhances process optimisation and failure analysis.

The latest integration of embedded JTAG solutions for the SPEA 3030 DualCore in-circuit tester (ICT) is aimed specifically at high-volume manufacturing test and supports parallel processing of multiple units under test (UUT). The goal is to significantly reduce cycle times while increasing test coverage and to ensure maximum efficiency of the test process.

Technical innovation for parallel test sequences

To meet the high demands of panel testing, the SPEA 3030 DualCore system is equipped with two fully independent ICT cores that can execute test sequences in parallel. A SCANFLEX II BLADE 8 RMx1-A/B/C with up to 8 TAPs and TIC modules from GÖPEL electronic are integrated into each ITC core, resulting in a maximum of 16 TAPs in the overall system.

This allows the user to process up to 16 PCBA in parallel. In addition to the standard JTAG port, SWD, SBW, BDM, and PIC are also supported, so that even non-JTAG components can be tested or programmed. The high degree of parallelization enables simultaneous execution of complex tests and significantly minimises test and programming times.

Thanks to the long-standing successful partnership between SPEA and GÖPEL electronic, users have access to a mature and proven hardware and software integration package. The integration of SCANFLEX hardware into the SPEA 3030 DualCore system provides a reliable and flexible platform that can be seamlessly integrated into existing production environments and ensures the highest quality test execution.