Corelis Launches Runner-Lite: The Free JTAG Test Executive

Runner-Lite is designed to provide engineers visibility, awareness, and accessibility to board level JTAG and functional testing. The Runner-Lite test executive applies boundary-scan test patterns to a reference board, reads back the responses, and provides comprehensive fault detection and isolation of boundary-scan chain infrastructure, board interconnect, pull-up/pull-down resistors, and clusters such as memories and UARTs. The tool also performs automated and interactive functional tests on peripheral components connected to the on-board processor as well as In-System-Programming (ISP) of CPLDs, Flash memories, and serial EEPROM devices.

The software includes a powerful graphical fault identification subsystem to isolate and visualize the location of PCB faults. The subsystem displays a CAD-based photographic representation of a reference design on the host PC display to facilitate the rapid discovery of the actual location for any failure, even when the fault is hidden underneath devices. This feature grants engineers the ability to visually locate the fault diagnostic area using the virtual PCB representation.

“Runner-Lite offers a simple and streamlined interface for companies looking to evaluate the capabilities of combined JTAG and functional based testing,” states Ryan Jones, Senior Technical Marketing Engineer at Corelis. “Users can download the software and execute a full suite of boundary-scan and functional tests in a matter of minutes.”

Runner-Lite offers unrestricted access to complete off-the-shelf JTAG structural and functional test solutions for many popular silicon vendor reference designs. It allows users to familiarize themselves with Corelis test capabilities and even use the tool as a test bench for their own reference board based designs. The software is offered at no charge and can be downloaded from the Corelis website.