Search results for "Synopsys"
Synopsys Extends HAPS Debug Visibility by 100X
Synopsys, Inc. today announced the release of a new Deep Trace Debug feature for users of its HAPS FPGA-based prototyping systems. With HAPS Deep Trace Debug, prototypers can take advantage of approximately 100 times more signal storage capacity than the traditional memory storage employed by on-chip FPGA logic debuggers.
Synopsys Introduces Proteus LRC for Lithography Verification
Synopsys Inc introduced Proteus LRC for lithography verification. Proteus LRC provides comprehensive, process-window-aware checking features to identify locations in a design that are sensitive to process variations, thereby enabling corrective action to be taken prior to committing a design to manufacture. Proteus LRC is integrated into the Proteus Mask Synthesis flow and is targeted for use by OPC and mask data preparation groups at semiconduct...
Lattice Design Tools Provide Complete 8-Bit Microcontroller System Support For Cost Sensitive, Low Power Pld Applications
Lattice Semiconductor announced release 1.2 of its Lattice Diamond FPGA design software tool suite, the flagship design environment for Lattice FPGA products. Users of the new MachXO2 PLD devices can now generate complete systems based on the LatticeMico8 open source 8-bit controller core using the LatticeMico™ System tool, which is available with the Lattice Diamond design environment.
New release of Lattice Diamond Design Software accelerates FPGA design optimization for lowpower and cost sensitive applications
Lattice Semiconductor Corporation today announced release 1.4 of its Lattice Diamond design software, the design environment for Lattice FPGA products. Users of Lattice Diamond 1.4 software will benefit from several usability enhancements that make FPGA design exploration easier and reduce time to market.
Synopsys unveils 30 percent smaller area, low power USB 2.0 PHY IP for 28nm processes
Synopsys, Inc has announced the addition of the new DesignWare USB 2.0 picoPHY IP to its USB 2.0 PHY IP product line that has been successfully deployed in more than 300 customer designs, and in more than 50 different process technologies ranging from 180nm to 32nm. Targeted at mobile and high-volume consumer applications such as feature-rich smartphones, mobile internet devices and netbooks, the DesignWare USB 2.0 picoPHY supports advanced 28nm ...
NetLogic Microsystems selects Synopsys as primary EDA partner
Synopsys has announced that NetLogic Microsystems, a leader in the design and development of knowledge-based processors and high speed integrated circuits, has signed an expanded business agreement to establish Synopsys as its primary EDA partner. NetLogic Microsystems chose Synopsys because of its technology leadership and its ability to help NetLogic Microsystems meet its aggressive product schedules.
Rockchip collaborates with Synopsys and Chartered to achieve first-pass silicon success
Fuzhou Rockchip Electronics Company, Ltd., Synopsys, Inc. and Chartered Semiconductor Manufacturing Ltd. today announced that Rockchip has achieved first-time silicon success on its next generation multimedia system-on-a-chip (SoC), using a combination of Synopsys’ tools, intellectual property (IP) and services with Chartered’s 65nm manufacturing technology. The RK28 multimedia SoC, Rockchip’s first mass-production 65nm chip designed in C...
ARM, Chartered, IBM, Samsung, and Synopsys Collaborate to Deliver Vertically Optimized Solution for 32/28nm Mobile SoC Designs
In a move that addresses fundamental challenges in creating advanced systems-on-chips (SoCs), ARM, Chartered Semiconductor Manufacturing Ltd. , IBM, Samsung Electronics, Co., Ltd., and Synopsys, Inc. (Nasdaq: SNPS) today announced at the Design Automation Conference (DAC) an agreement to develop a comprehensive technology enablement solution for the design and manufacture of mobile Internet-optimized devices. The objective of this collaboration i...
Synopsys' DesignWare SuperSpeed USB 3.0 IP Achieves More Than 40 Design Wins
Synopsys announced that its DesignWare SuperSpeed USB 3.0 IP has surpassed 40 SoC design wins and more than 30 customer licensees worldwide. Because Synopsys' DesignWare USB 3.0 Digital Core and PHY IP has been broadly adopted by leading semiconductor companies targeting a variety of applications and process technologies, designers can be confident the IP is silicon-proven and can lower their SoC integration risk.
Snopsys Unveils Virtualizer Development Kits to Accelerate Software Development for ARM big.LITTLE Processing
Synopsys, Inc. today announced the first release of the Virtualizer Development Kit (VDK) Family for accelerating software development. The VDK Family for ARM Cortex Processors contains multiple reference designs, analysis and debug software tools for the Cortex-A15 MPCore processor and ARM big.LITTLE processing. By using the VDKs developers can now optimize for performance and energy efficiency prior to board availability. The reference designs ...