Search results for "Synopsys"
Synopsys accelerates development of SoC designs with complete IP solution for PCI Express 3.0
Synopsys has announced its complete DesignWare IP solution for PCI Express 3.0 consisting of digital controllers, PHY and verification IP. PCI Express 3.0 is the next generation of the PCI Express I/O standard, which is currently under development within the PCI Special Interest Group (PCI-SIG(r)) at a preliminary revision 0.5. Synopsys' high-quality DesignWare IP enables easy integration of the 8.0 GT/s PCI Express 3.0 interface into system-on-c...
Synopsys Unveils Galaxy Characterization Solution for Standard Cells, Complex Macros and Memories
Synopsys introduced its Galaxy Characterization Solution. The Galaxy Characterization Solution is a comprehensive suite of tools architected to generate compact, highly-accurate libraries for the design and implementation of complex system-on-chips (SoCs). Today's SoCs require libraries that contain hundreds of gigabytes of timing, power, noise and process variation data to ensure the chip meets all performance criteria. The Galaxy Characterizati...
Synopsys Delivers Optimized Lynx Design System for Common Platform 32/28-nm Technology
Synopsys announced it is delivering an optimized, pre-validated design environment for the Common Platform alliance (CPA) 32/28-nanometer(nm) high-k metal gate (HKMG) technology based on Synopsys' Lynx Design System.
Synopsys First to Deliver High-Performance Audio IP in 40-nm and 55-nm Process Technologies
Synopsys announced the addition of the DesignWare 96 dB Hi-Fi Audio IP in the 40-nanometer (nm) and 55-nm process technologies to its broad portfolio of high-quality audio IP solutions. Synopsys is the first IP provider to offer audio codecs, digital-to-analog converters (DACs) and analog-to-digital converters (ADCs) in these advanced processes. The DesignWare Audio IP portfolio offers performance levels from 80 dB to 103 dB and is available in ...
Synopsys Adds TDD Support to LTE Model Library
Synopsys, Inc. today announced the availability of the Time Division Duplex (TDD) mode in its Long-term Evolution (LTE) Model Library for physical layer system simulation. The addition of the TDD mode to the proven LTE Model Library enables developers of semiconductors for LTE network equipment and devices to quickly and reliably extend their designs to support this important version of the 3rd Generation Partnership Project (3GPP) LTE standard.
Synopsys launches MIPI DigRF v4 IP & speeds LTE and WiMAX SoC development
Synopsys announced the immediate availability of the DesignWare MIPI 4G DigRF(SM) Master Controller IP. By complementing its current silicon-proven DesignWare MIPI 3G DigRF Controller and PHY IP, Synopsys becomes the first vendor to offer a comprehensive IP portfolio for both the MIPI DigRF v3 and v4 standards.
Synopsys Unveils Ethernet Controller IP With New Audio Video Bridging Feature
Synopsys announced the immediate availability of the DesignWare Ethernet Quality-of-Service (QoS) Controller IP which implements the new IEEE specifications for audio video bridging (AVB) features. The DesignWare Ethernet IP solution supports the new IEEE 802.1AS and 802.1-Qav version D6.0 specifications.
Synopsys DesignWare DDR multiPHY IP supports six DDR standards in a single PHY
Synopsys, Inc. today announced availability of the DesignWare DDR multiPHY which is designed to support a broad range of DDR SDRAM standards in a single PHY without sacrificing power consumption or silicon area. These standards include LPDDR2, LPDDR/Mobile DDR, DDR3, DDR3L (1.35 V), DDR3U (1.2x V), and DDR2. The DesignWare DDR multiPHY enables designers to target different DDR types for a single chip through simple software control. This capabili...
Synopsys' DesignWare STAR ECC IP Helps Reduce Embedded Memory Transient Errors
Synopsys announced the availability of the DesignWare STAR ECC (Self-Test and Repair Error Correcting Codes) IP as a part of its DesignWare STAR Memory System® product family. The new DesignWare STAR ECC IP offers a highly automated design implementation and test diagnostic flow that helps system-on-chip (SoC) designers to quickly reduce the number of embedded memory transient errors, such as soft errors, that occur in emerging semiconductor pro...
Synopsys HSPICE Precision Parallel technology delivers up to 7X speed-up for analogue/mixed-signal designs
Synopsys unveiled new HSPICE(r) Precision Parallel (HPP) multi-threading technology that delivers up to 7X simulation speed-up for complex analogue and mixed-signal designs. In addition to the new HPP technology, the HSPICE 2010 solution includes enhanced convergence algorithms, advanced analogue analysis features and foundry-qualified support for process design kits (PDKs) that extend HSPICE gold-standard accuracy to the verification of complex ...