Search results for "Synopsys"
Mazda Adopts Synopsys' Virtual Prototyping Solution for Electronic Control Unit Verification
Synopsys, Inc. announced that Mazda Motor Corporation, a leading producer of automobiles, has adopted Synopsys' CoMET-METeor virtual prototyping solution to verify their Electronic Control Units (ECUs). Over the last year, Mazda has been using the METeor embedded software development environment to conduct its ECU system verification in a virtual environment. By decreasing the number of tests on real automobiles and hardware-in-the-loop simula...
Synopsys Honors Shrenik Mehta with Eleventh Annual Tenzing Norgay Interoperability Achievement Award
Synopsys announced today that Shrenik Mehta has been awarded Synopsys' eleventh annual Tenzing Norgay Interoperability Achievement Award. As chairperson of Accellera, a leading standards organization in electronic design automation (EDA), from 2005 until 2010, Shrenik guided the organization to several collaborative initiatives that created widely-used standards such as SystemVerilog, Unified Power Format (UPF), and Universal Verification Methodo...
Synopsys Reduces IP Integration Risk With Extensive SATA-IO Interoperability Testing
Synopsys today announced that Synopsys' DesignWare® Serial Advanced Technology Attachment (SATA) IP solution has successfully passed the SATA International Organization (SATA-IO) electrical, digital and system interoperability testing for 130- to 40-nanometer (nm) process technologies. The SATA-IO interoperability testing validates Synopsys' internal testing of the DesignWare SATA IP, which includes extensive digital and mixed-signal simulation ...
Synopsys Posts Financial Results for Fourth Quarter and Fiscal Year 2010
Synopsys today reported results for its fourth quarter and fiscal year 2010. For the fourth quarter of fiscal 2010, Synopsys reported revenue of $375.5 million, compared to $338.3 million for the fourth quarter of fiscal 2009. Revenue for fiscal year 2010 was $1.38 billion, an increase of 1.5 percent from $1.36 billion in fiscal 2009.
Synopsys and Virage Logic Announce Expiration of Hart-Scott-Rodino Waiting Period for Proposed Acquisition
Synopsys, Inc. (Nasdaq: SNPS) and Virage Logic Corporation (Nasdaq: VIRL) announced today that the 30-day waiting period under the Hart-Scott-Rodino Antitrust Improvements Act of 1976, applicable to Synopsys' proposed acquisition of Virage Logic, expired on July 19, 2010.
Synopsys Replenishes Stock Repurchase Authorization to $500 Million
Synopsys today that its board of directors has replenished its stock repurchase authorization. Under the replenished program, the company may repurchase Synopsys common stock with a market value up to $500 million.
Synopsys Acquires ExpertIO
Synopsys, Inc. announced today that it has closed the acquisition of ExpertIO, Inc. The addition of ExpertIO's team of protocol experts and its strong portfolio of storage VIP will accelerate Synopsys' delivery of a broad line-up of high-performance, easy-to-use, full-featured VIP that can help designers address their growing verification challenges. The terms of the deal have not been disclosed.
Synopsys Appoints Dr. C.L. Max Nikias to its Board of Directors
Synopsys announced the appointment of Chrysostomos L. Max Nikias to its Board of Directors, effective July 11, 2011. Dr. Nikias is the current President of the University of Southern California (USC), a position he has held since August 2010, and holds the Robert C. Packard President's Chair and the Malcolm R. Currie Chair in Technology and the Humanities.
Lattice Improves Synthesis And Power Optimization In CPL Design Tools
Lattice Semiconductor today announced the immediate availability of Version 1.4 of its ispLEVER® Classic design tool suite. The ispLEVER Classic design software has been upgraded with the addition of Synopsys Synplify Pro with the HDL Analyst feature set, and an improved ispMACH® 4000ZE CPLD fitter with improved power optimization.
Updated Lattice Diamond Fpga Design Software Supports New MachXO2 PLD Family
Lattice Semiconductor Corporation today announced Version 1.1 of its Lattice Diamond FPGA design software, the flagship design environment for Lattice FPGA products. This important update includes support for the new MachXO2™ PLD family, completion of support for the LatticeECP3™ FPGA family, and the initial release of Lattice’s own synthesis engine with support for the MachXO™ and MachXO2 product families.