Search results for "Synopsys"
Synopsys' IC Validator Completes Qualification for TSMC's 40-nm and 65-nm iDRC/iLVS Physical Verification
Synopsys announced that its IC Validator physical verification product is qualified for TSMC's 40-nm and 65-nm interoperable DRC/LVS runsets, and is immediately available to TSMC customers. IC Validator, part of the Galaxy™ Implementation Platform, is an ideal add-on to IC Compiler for In-Design physical verification. By enabling physical verification within the implementation flow, IC Validator enables place and route engineers to accelerate t...
Synopsys Galaxy Implementation Platform Addresses Gigascale Design
Synopsys announced the 2010.12 release of its Galaxy Implementation Platform, delivering new technologies to address the scalability, convergence and throughput needs of Gigascale design. Faster runtime performance with multicore processing and innovations to increase design capacity throughout the Galaxy Platform enable engineering teams to gain productivity benefits for large-scale, complex integrated circuit (IC) design. Additionally, the Gala...
Latest Release of Synopsys IC Compiler Delivers Faster Design Closure
Synopsys announced the availability of the latest release of IC Compiler, a key component of the Galaxy Implementation Platform. This development caps a year of leading innovations in physical design productivity. For two years in a row, IC Compiler has won an EDN Innovation Award. In 2010 it won for In-Design Physical Verification. The IC Compiler 2010.12 release advances this capability, making automatic DRC repair up to 7X faster. This latest ...
Synopsys' DesignWare Universal DDR Memory Controller Delivers up to 30 Percent Lower Latency and Increases System Performance
Synopsys announced the release of its enhanced DesignWare Universal DDR Memory Controller, which delivers up to 30 percent lower latency and offers up to 15 percent higher throughput than the previous generation controller. The DDR Memory Controller offers new features such as high-priority bypass and configurable 'look-ahead.' The high-priority bypass option allows designers to improve latency by bypassing the scheduling algorithm, allowing imme...
Synopsys' CODE V Enhances Aspheric Lens System Design
Synopsys, Inc. today announced the availability of enhancements to its CODE V optical design and analysis software.
Synopsys extends DFTMAX compression to reduce the cost of pin-limited test
Synopsys has announced a new capability in DFTMAX compression that significantly reduces the cost of test for designs and methodologies that mandate very few test pins. Extending Synopsys’ patented adaptive scan technology with a high-performance, low-pin interface to the tester allows designers to achieve predictable compression of up to 100X or more with only one pair of test data pins. As designers must maintain test quality and reduce test ...
Synopsys Collaborates with Sigrity to Accelerate Signal Integrity Analysis
Synopsys, Inc. and Sigrity, Inc. today unveiled an enhanced solution that accelerates signal integrity simulation of high-speed systems. In the latest release of the HSPICE circuit simulator, Synopsys has employed in-memory communication to deliver deeper integration with Sigrity's signal integrity analysis offerings.
Synopsys delivers unified solution for digital and custom SoC designs
Synopsys, Inc. announced advances in its Galaxy Implementation Platform with the availability of its unified solution for mixed-signal designs. The new unified solution provides seamless integration between IC Compiler physical implementation and the Galaxy Custom Designer solution, allowing design teams to easily move between digital and custom implementation flows while maintaining design data integrity. The unified solution accelerates the des...
Lattice FPGA Design Tool Suite Includes Advanced Support for High Performance DDR Interfaces
Lattice Semiconductor has announced Version 8.0 of its ispLEVER FPGA design tool suite, which includes many enhancements for the design of high speed double data rate (DDR) interfaces for the LatticeECP3 FPGA family. These enhancements include automatic interface code generation to increase design productivity and reduce coding errors, as well as enhanced timing analysis that provides more transparency to circuit timing details.
Magma Appoints Noriaki Kikuchi President of Japanese Subsidiary
Magma Design Automation Inc. (Nasdaq: LAVA), a provider of chip design software, announced today it has named Noriaki Kikuchi president of Magma KK, Magma’s Japanese subsidiary. Kikuchi, with more than 30 years experience in electronic design automation and other technology industries, reports to Magma President and Chief Operating Officer Roy E. Jewell.