Search results for "EDA"

Cadence Design Systems Inc detailed the extensive expansion of its broad portfolio of verification IP and memory models, which delivers a robust verification solution spanning silicon, SoC and system development. The Cadence VIP offering boasts support of new protocols such as ARM AMBA 4 and MIPI to address early IP verification and integration through to system validation in demonstration of the EDA360 vision. In addition to memory models and VI...

Cadence Design Systems today laid out a new vision for the semiconductor industry, EDA360. In outlining an application-driven approach to system design and development, Cadence issued a challenge to the semiconductor and electronic design automation (EDA) communities to address the growing “profitability gap” that threatens the vitality of the electronics industry.

Cadence Design Systems introduced the latest version of its Allegro PCB and IC packaging technology, delivering new capabilities that provide a significant increase in both productivity and predictability across silicon, SoC and system development.

Cadence Design Systems today announced that Robert Bosch GmbH (Bosch) has standardized on an enhanced custom/analog flow based on Cadence® Virtuoso® v6.1 technology, gaining approximately a 25 percent advantage in productivity for advanced custom/analog silicon design.

Cadence Design Systems today is celebrating Innovation Day, honoring the contributions Cadence employees have made to the company and the electronics industry as a whole. Having garnered more than 800 U.S. patents and an additional 150 international patents, Cadence has a long legacy of technology innovation that has enabled EDA customers to successfully create some of the world’s most recognized consumer and business products for over 20 years...

Cadence Design Systems today announced that Spreadtrum Communications (NASDAQ: SPRD), a leading provider of baseband and RF processor solutions for the wireless communications market headquartered in Shanghai, migrated to the Cadence® Silicon Realization flow and successfully taped out its first 40-nanometer low-power chip. The chip, a GSM/GPRS/EDGE/TD-SCDMA/HSPA mobile phone baseband, was taped out with one-pass silicon success.

Cadence Design Systems today announced that Semiconductor Manufacturing International Corporation (SMIC, NYSE: SMI and SEHK: 981), the largest semiconductor foundry in China, has adopted Cadence® Silicon Realization products for the design-for-manufacturing (DFM) and low-power technology at the core of SMIC’s 65-nanometer Reference Flow 4.1. Using Cadence Encounter Digital Implementation System as the foundation, the companies collaborated to ...

Cadence Design Systems today announced that Global Unichip Corporation (GUC) has adopted the Cadence® Encounter® Timing System to reduce time to final design closure efficiently in its Encounter Digital Implementation (EDI) System-based design flows. By adopting the integrated signoff solution, GUC is able to shorten lead time and reduce tapeout schedule risk for Silicon Realization.

Cadence announced it has acquired Azuro, Inc., a company that has pioneered a paradigm shift in the digital implementation and optimization of next-generation SoCs. Azuro offers unique clock concurrent optimization technology, also known as ccopt, which delivers superior capabilities for designers faced with increasing performance, power and area challenges.

Accelerated Designs Inc. (ADI), a PCB Library Software and Services firm headquartered in Huntsville, AL has completed a project to link their Ultra Librarian ( UL ) tool to the Premier Farnell DesignLink system. The DesignLink system is an electronic interface to the Premier Farnell electronics parts databases of Newark, Farnell, and Premier Electronics spanning Europe, the Americas and Asia Pacific.