Search results for "TSMC"

Cadence Design Systems, Inc. today announced that its Encounter digital and Virtuoso custom/analog design platforms achieved TSMC Phase I certification for 20-nanometer design, implementation and verification/signoff. TSMC certified the tools for 20-nanometer design rule manuals and SPICE models.

Magma Design Automation Inc. (Nasdaq: LAVA), a provider of chip design software, today announced that TSMC has selected Quartz DRC and Quartz LVS for physical verification in TSMC’s Integrated Sign-off Flow (ISF). TSMC provides certified flow comprising proven, best-in-class tools to enable the fastest path to TSMC silicon. The flow is now available for 65-nanometer (nm) designs.

At the International Electron Devices Meeting in San Francisco imec’s advanced CMOS research program reports promising advances in scaling logic, DRAM and non-volatile memory. A new device based on non-silicon channels was realized to scale high-performance logic towards the sub-20nm node. Moreover, imec developed low-leakage capacitors allowing DRAM to be pushed to the 2x nm node. And the switching mechanism of resistive RAM for next-generatio...

Imec sets major step towards 20nm half pitch interconnects with the realization of electrically functional copper lines embedded into silicon oxide using a spacer-defined double patterning approach.