Search results for "EDA"

Engineers working on the design of power delivery networks will benefit from CST’s latest addition to CST STUDIO SUITE. The new CST PCB STUDIO Power Integrity solver, based on a special 3D FEM approach, helps calculate accurate impedance profiles within a full 3D simulation, but in a fraction of the time required by traditional 3D solvers.

Imec, a world-leading nanoelectronics research institute based in Belgium, and Cadence Design Systems announced new technology that delivers an automated test solution for design teams deploying 3D stacked ICs (3D-ICs). The technology addresses the test challenges involved as electronics companies increasingly turn to 3D-ICs as a way to increase circuit density and achieve better performance at lower power dissipation for mobile and other applica...

Cadence Design Systems today advanced the design of giga-gate/gigahertz system on chips (SoCs) with a proven digital end-to-end flow at 28 nanometers that yields both performance and time-to-market advantages. Driven by the Cadence Silicon Realization approach, the new Encounter-based flow provides a faster, more deterministic path to achieve giga-gate/gigahertz silicon through technology integration and significant core architecture and algorith...

Cadence Design Systems, Inc. (NASDAQ: CDNS), a leader in global electronic design innovation, today announced that Global Unichip Corporation (GUC) has adopted Cadence® Virtuoso® custom design technologies to speed development of its high-speed interface IP. GUC also has adopted Cadence design for manufacturing (DFM) technologies for its advanced process node system-on-chip (SoC) designs.

Cadence Design Systems, Inc. today announced that the company’s comprehensive suite of DDR controller and DDR PHY design IP as well as its Cadence Verification IP Catalog now support the latest release of the DFI specification, version 3.1. The new version adds support for the LPDDR3 mobile memory standard for smartphones and tablets, and includes enhancements to the PHY’s low-power interface and training features.

Cadence Design Systems today announced that the most advanced foundry in Mainland China, Semiconductor Manufacturing International Corporation (“SMIC”, NYSE: SMI and SEHK: 0981.HK), has adopted the Cadence Silicon Realization product line for advanced node, low-power designs. The Cadence Silicon Realization product line is composed of tools essential to turning designs into silicon. It is a key element of its EDA360 (the new Electronic Design...

Cadence reported first quarter 2011 revenue of $266 million, compared to revenue of $222 million reported for the same period in 2010. On a GAAP basis, Cadence recognized net income of $6 million, or $0.02 per share on a diluted basis in the first quarter of 2011, compared to a net loss of $12 million, or $(0.04) per share on a diluted basis, in the same period in 2010.

Microdul AG has adopted an integrated mixed-signal flow from Dolphin Integration and Tanner EDA. The solution brings together HiPer Silicon, Tanner EDA's analog design suite, with SMASH, Dolphin Integration's logic and mixed-signal simulator, to provide an affordable and innovative mixed-signal EDA flow that operates smoothly from design capture to verification. Microdul benefits from a state-of-the-art design flow that ensures compatibility with...

Tanner EDA, the catalyst for innovation for the design, layout and verification of analog and mixed-signal integrated circuits (ICs) and IC Mask Design, an industry leader in the provision of physical design services to the global semiconductor industry, are collaborating on the development of a toolset to accelerate analog layout design. By exclusively licensing IC Mask Design's patented layout acceleration technology and integrating it into Tan...

Silicon Frontline Technology announced today that since the May introduction of the company and its first products, F3D (Fast 3D) for fast 3D extraction and R3D (Resistive 3D) for 3D extraction and analysis of large resistive structures, the company has achieved success and validated its position as a player in the post-layout verification and 3D extraction markets.