Search results for "ASIC"
UltraSoC selected for safety applications across ARM platforms
UltraSoC has announced that ELVEES has licensed UltraSoC’s embedded analytics technology for use in its next-gen video processing offerings. The new ELVEES System on Chip (SoC) product will provide advanced capabilities for a broad range of applications, from automotive safety and ADAS (Advanced Driver Assistance Systems), to facial recognition, augmented/virtual reality and vision based IoT systems.
Converged network for industrial IoT
Implementing a scalable, secure network system across a factory environment can result in savings in cost of implementation while increasing flexibility, write Michael Zapke, Xilinx, and embedded systems consultant, Adam Taylor
Evaluation kit delivers rapid IoT prototypes
The Grid-EYE evaluation kit from Panasonic is available at Mouser Electronics. By combining Grid-EYE infrared (IR) sensor technology with Bluetooth technology and software for IR detection of people and objects on one board, the kit enables engineers to develop rapid prototypes of wireless sensor Internet of Things (IoT) applications.
25A µModule regulator supports N+1 redundancy
Analog Devices who recently acquired Linear Technology, has announced the LTM4645, a 25A step-down µModule regulator with the ability to current share multiple independent devices (N) where at least one LTM4645 is used as backup (+1) to ensure power availability if one device in this N+1 arrangement detects a fault and must be disconnected.
MPUs support digital encoder interface for AC servo applications
Supplier of advanced semiconductor solutions, Renesas Electronics, has announced a new solution package for its RZ/T1 Group of microprocessors (MPUs) supporting HIPERFACE DSL digital encoder interface for AC servo applications. The support of HIPERFACE DSL for RZ/T1 reduces the customer’s system bill-of-materials (BOM) cost and enables faster time-to-market.
Simulator improves performance speedup on mixed-signal design
In order to accelerate ASIC development for delivery of its automation equipment for test and industrial applications, Cadence Design Systems has announced that Teradyne has standardised its simulation tasks using the Xcelium Parallel Logic Simulator. With the Xcelium simulator, Teradyne achieved a two times performance speedup with production-use single-core, mixed-signal ASIC verification when compared with its previous simulation solution.
DCM DC/DC converters in ChiP package with ±1% regulation
Vicor have extended its family of isolated, regulated DC/DC converter modules (DCMs) in ChiP packages, with a range of components that offer ±1% voltage regulation.The new series of DCMs are initially offered with 28, 270, and 275V nominal input voltages. These products are aimed at a variety of applications that require tighter output voltage regulation, including UAV, ground vehicle, radar, transportation and industrial controls.
Eliminating the Last Inch with Power on Package
Vicor has announced the Power on Package technology that enables manufacturers of CPUs, GPUs and ASICs (XPUs) to place power components either on the substrate of their device (on package) or extremely close to the XPU socket. Eliminating the “last inch” between the regulator and the XPU makes possible the level of higher performance required for today’s most demanding applications.
Compact linear encoder suitable for feedback applications
A new, miniature, exposed linear encoder system has been introduced by HEIDENHAIN with the capability of resolving to 2nm. This performance is maintained at high traverse speeds up to 240m/min over long scale lengths to a maximum of 3,040mm. Machine builders in the semiconductor manufacturing, metrology and micromachining sectors are prospective users.
Solution improves multi-functional printer SoCs design development
In order to improve the development of its multi-functional printer SoCs, Fuji Xerox used Cadence Design Systems' Cadence Genus Synthesis Solution. The Cadence solution enabled Fuji Xerox to reduce its timing closure schedule more than 50% and achieve up to 16% area reduction for its sub-blocks, resulting in an eight percent total chip area reduction when compared with its previous solution.