Search results for "Synopsys"

Synopsys says it has distributed 3000 copies of its Better Software, Faster! book on virtual prototyping to more than 1000 companies. The fast adoption of the book demonstrates how the industry is increasingly looking to virtual prototyping as a method to help develop software much earlier in the design cycle and accelerate project schedules.

A USB 3.1 IP solution, consisting of Synopsys DesignWare USB 3.1 Device Controller, an IP Virtual Development Kit (VDK) and verification IP (VIP) has been designed to accelerate the development of high-performance storage, digital office and mobile system-on-chip (SoC) applications.

Panasonic’s LSI Business Division has achieved first time working silicon using the Synopsys IC Compiler II designed for high-performance multimedia design in 40-nm technology. Compiler II offers 5X faster design implementation that enables faster turn-around-time for large partitions. It has the ability to seamlessly handle more modes and corners drastically improves signoff convergence and reduces ECO iterations.

Synopsys has availability of the silicon-proven DesignWare AEON Few Time Programmable (FTP) Trim Non-Volatile Memory (NVM) IP for TowerJazz 180-nanometer (nm) SL process technology. The NVM IP integrates high voltage generation and control circuitry using a standard CMOS technology without the need for additional masks or processing steps.

Chip maker SK Hynix has addressed their debug challenges by adopting the Synopsys VC Apps open application programming interfaces (APIs) to directly link their internally developed test generation technology to the Synopsys Verdi debug solution and allow their design and verification teams to customise their debug experience and boost debug productivity.

Synopsys has signed a multi-year OEM agreement with Gowin Semiconductor for Synopsys Synplify Pro FPGA synthesis tools. The agreement will enable Gowin customers to improve synthesis runtimes and achieve higher quality of results for timing, area and power for Gowin GW2A/3S FPGAs.

Synopsys' IC Validator product has been certified by SMIC for signoff physical verification of their 28nm PolySiON (PS) manufacturing process. This provides mutual customers with access to a wider selection of signoff tools for physical verification. Fully qualified Design Rule Checking (DRC) and Layout-Versus-Schematic (LVS) runsets are available for download from the SMIC website.

To achieve a 10% reduction in total die size while maintaining product quality and performance, Marvell Semiconductor have utilised Synopsys'MMB (Multi-Memory Bus) processor for it's networking SoC. The processor, from Synopsys' DesignWare STAR Memory System, allowed Marvell to accelerate silicon bring-up and achieve silicon success.

Synopsys will host its annual Test Special Interest Group (SIG) event during the International Test Conference (ITC) 2014 in Seattle (Oct 21-23). Delegates will hear a plenary keynote speech from Synopsys Chairman and co-CEO Dr. Aart de Geus, and be able to attend numerous technology sessions featuring Synopsys test experts throughout the three-day conference.

Synopsys says that VIA Technologies has successfully taped out a system-on-chip (SoC) design using Synopsys' DFTMAX Ultra compression, meeting test time and quality goals. The need to shorten test time in conjunction with increasing design complexity drove VIA Technologies requirement for higher test compression. DFTMAX Ultra and Synopsys' TetraMAX ATPG delivered 11X higher compression while maintaining high test quality and requiring only one we...