Search results for "Synopsys"

ams has announced the availability of its first interoperable process design kit (iPDK) for its 0.35μm analogue speciality processes. iPDKs are based on the OpenAccess database and use standard languages as well a unified architecture to enable interoperability among multiple EDA vendor tools.

Synopsys and Intrinsic-ID have announced the integration of Intrinsic-ID's PUF technology with Synopsys' DesignWare ARC EM Processors with SecureShield technology to enable efficient implementation of security functions such as authentication and device cloning prevention for low-power IoT edge devices.

Synopsys has announced a collaboration with Cypherbridge Systems to optimise Cypherbridge's uSS software development kit (SDK) for the Synopsys DesignWare SSL/TLS/DTLS Security Protocol Accelerator (SPAcc). The joint solution enables the offload of cryptographic functions to dedicated hardware, giving system architects the ability to reallocate the CPU to other functions or use a smaller CPU.

Synopsys' IC Validator physical verification product has been certified by Samsung Foundry for all designs using its 14nm manufacturing processes, Samsung Foundry's most advanced technology currently in production.

It has been announced that the circuit simulators from Synopsys will include a native environment for simulation management and analysis. Available in the 2016.03 release of HSPICE, FineSim and CustomSim simulators, the environment provides a comprehensive solution that improves analogue verification productivity.

Synopsys has announced that it is the first to achieve SuperSpeed USB 10 Gbps (USB 3.1 Gen 2) IP certification from the USB Implementers Forum (USB-IF). To attain certification, the Synopsys DesignWare USB 3.1 Controllers and PHYs passed all of the USB-IF protocol, electrical and interoperability tests for SuperSpeed USB 10 Gbps (USB 3.1 Gen 2), SuperSpeed USB (USB 3.1 Gen 1) and Hi-Speed USB (USB 2.0, 480 Mbps).

Synopsys announces what is claimed to as the industry's first VIP to support the SAS (Serial-attached SCSI) 24G standard, making it the first VIP product line to support all SAS interface speed configurations. With increasing demands for the storage, backup and transmission of data, enterprise storage systems are challenged to rapidly transmit data across devices. Synopsys VC VIP for SAS delivers a comprehensive VIP solution, enabling SoC teams t...

Synopsys has announced the DesignWare Smart Data Fusion IP Subsystem, an integrated, pre-verified hardware and software IP product optimised for highly efficient DSP performance and ultra-low energy consumption. The Smart Data Fusion IP Subsystem offers a choice of DesignWare ARC EM DSP processors, including the latest EM9D and EM11D cores with support for XY memory to boost signal processing performance.

Synopsys has introduced the DesignWare USB-C 3.1/DisplayPort 1.3 IP solution which integrates USB Type-C (USB-C), SuperSpeed USB 10Gb/s (USB 3.1 Gen 2) and DisplayPort 1.3 interfaces with High-bandwidth Digital Content Protection (HDCP) 2.2 IP. The solution accelerates development of mobile and digital office SoCs that require 10Gb/s data transfer and delivery of secure audio/video content and power through a single USB Type-C connector.

The 2015.12 release of Synopsys' StarRC solution delivers key technology innovations to address the increasing parasitic extraction and signoff challenges arising from Moore's Law scaling continuation. The new innovations significantly raise the bar on performance and scalability, while providing an improved architecture designed to leverage mainstream or leading-edge compute resources more efficiently.