Search results for "Synopsys"

Synopsys has announced the extension of its Safety Enhancement Package (SEP) to DesignWare ARC EM processors that include cache support and DSP acceleration. The ARC EM4, EM6, EM5D and EM7D cores, combined with the ARC SEP option, have been certified ASIL D Ready by SGS-TÜV Saar, a leading independent certification company.

Cadence Design Systems has announced that Tezzaron Semiconductor has adopted the Cadence full-flow digital Register-Transfer Level (RTL)-to-signoff solution for its networking and supercomputing SoCs, cutting its development schedules in half. Tezzaron has incorporated Cadence tools in its design work from the very beginning. Over the years, Tezzaron’s products have increased in size, sophistication and complexity, prompting the adoption of...

Synopsys has announced its next-gen VIP (Verification IP) for Micron's Hybrid Memory Cube (HMC) architecture. The HMC architecture offers a high performance, low cost memory solution, with 70% less energy utilisation than existing DRAM technologies. Synopsys VC VIP for HMC enables the design of next-generation high-speed memory technologies with ease of use, fast integration and optimum performance, resulting in accelerated verification closure.

Interoperable Process Design Kits (iPDKs) are now available from Dongbu HiTek and Synopsys that enable Dongbu HiTek foundry customers using Synopsys’ Custom Compiler solution to rapidly design specialised analogue/power and mixed signal chips that target high growth markets.

Synopsys has announced immediate availability of the industry's first MIPI I3C controller IP to ease the integration of multiple sensors into applications such as mobile, automotive and the IoT. The Synopsys DesignWare MIPI I3C Controller IP incorporates in-band interrupts within the 2-wire interface to deliver low pin count.

Micronas has deployed ClioSoft’s SOS7 Design Management Platform. ClioSoft is the pioneer and leading developer of SoC design configuration and enterprise IP management solutions for the semiconductor industry. ClioSoft’s SOS platform is integrated with major EDA flows from Cadence Design Systems, Keysight Technologies, Mentor Graphics and Synopsys.

Synopsys has announced the expansion of its VC Verification IP (VIP) portfolio with CAN 2.0/FD/TT (ISO 16845 compliant), LIN, FlexRay and Ethernet Audio Video Bridging (AVB) protocols for the verification of automotive applications. These verification IP titles include test suites and spec-linking technology required to verify compliance to automotive standards.

Synopsys has announced that UL has selected Synopsys' software security testing tools for use in the recently launched UL Cybersecurity Assurance Program (CAP). The UL CAP is an international certification programme that provides independent third-party security assessment of network‐connectable devices in accordance UL 2900, a series of cybersecurity standards developed with input from a large group of stakeholders, including the U.S. Departme...

To address the challenges of timing and power closure for FinFET designs, Synopsys has released the 2015.12 release of the PrimeTime static timing analysis tool. New PrimeTime technology improves turnaround time and power reduction while providing smarter utilisation of compute resources. This software release helps chip designers to meet demanding sign-off schedules at advanced process nodes.

Synopsys has unveiled Custom Compiler, a custom design solution that closes the FinFET productivity gap by shortening custom design tasks from days to hours. To bring new levels of productivity to FinFET layout, Synopsys has taken a fresh approach to custom design by developing visually-assisted automation technologies that speed up common design tasks, reduce iterations and enable reuse.