Search results for "EDA"

Signing a definitive agreement, Synopsys is to acquire Atrenta. By integrating Atrenta's complementary static verification and implementation technology with Synopsys' Verification Continuum and Galaxy Design platforms, Synopsys can offer designers a more comprehensive, robust portfolio of silicon to software solutions for today's complex electronic systems.

Designed to help SoC integrators secure the operations of RF blocks, the nLR-Charny low-noise linear regulator has been released by Dolphin Integration. The device, which meets stringent low noise requirements, is suitable for use with a wide range of standard cells, memories and power regulators to meet the challenges of embedded low power voltage domains.

Targeting applications requiring a high level of processing per MHz and low power consumption in a small footprint, the the eSI-32X0MP scalable, asymmetric multicore processor has been released by EnSilica. The processor, which expands the company’s eSi-RISC family, is suitable for WiFi, LTE Cat-0 and other IoT standards as well as scalable sensor, Gbit security protocol and solid state disk levelling algorithm processing.

Steve Rogerson reports from Cadence’s CDN Live user conference in Munich.

Mentor Graphics has announced that TSMC and Mentor Graphics have reached the first milestone of their collaboration on 10nm EDA certification.Calibre physical verification and Design For Manufacturing (DFM) platform, and theAnalog FastSPICE (AFS) Circuit Verification Platform, including AFS Mega, are certified by TSMC based on the most current version of 10nm design rules and SPICE models.

In a bid to bring unity to a disparate process, Mentor Graphics has officially launched a tool that allows designers to work at the chip, package and PCB level concurrently.

The E-Seal range of ingress protected (IP) connectors has been enhanced by EDAC Europe with the introduction of new water, mist and dust-proof wire-to-board and in-line plug & socket connectors. The IP code is used to define the level of environmental protection provided by electrical equipment enclosures.

As designs become more complex and time-to-market schedules become more demanding, engineers must take advantage of pre-layout simulation and simultaneous process design in order to beat the competition. By Barry Olney, CEO, In-Circuit Design Pty Ltd.

Cadence Design Systems has announced that its digital and custom/analogue tools have achieved certification from TSMC for its most current version of 10nm FinFET Design Rule Manual (DRM) and SPICE models.The custom/analogue and digital implementation and signoff tools have been certified by TSMC on high-performance reference designs in order to provide customers with the fastest path to design closure on the 10nm FinFET process.

Keysight Technologies’ Advanced Design System PCI Express and USB Compliance and Test Benches enable a complete workflow for SerDes engineers, from simulation of a candidate design, through measurement of the finished prototype. The solution is ideal for semiconductor companies developing SerDes I/O blocks and OEMs integrating such chips onto their system PCBs.