Search results for "Synopsys"
Next gen ATPG shortens test pattern generation from days to hours
The next gen ATPG and diagnostics solution, TetraMAX II by Synopsys, incorporates the innovative test engines unveiled at the International Test Conference in October 2015. Delivering an order of magnitude faster runtime, TetraMAX II cuts ATPG runtime from days to hours, ensuring patterns are ready when early silicon samples are first available for testing.
ATPG tool provides highest level of safety-related tool confidence
It has been announced by Synopsys that its TetraMAX II Automatic Test Pattern Generation (ATPG) tool delivering 10 times faster run time and 25% fewer test patterns, is now certified for the ISO 26262 automotive functional safety standard. SGS-TÜV Saar GmbH, an independent accredited assessor, formally certified TetraMAX II, following an in-depth functional safety tool qualification.
ATPG engines speed test generation for SoC designs
Synopsys has announced that STMicroelectronics is seeing significantly faster test pattern generation runtime and reduced number of patterns with TetraMAX II ATPG. STMicroelectronics faces the challenges of increasing complexity and shrinking time-to-market schedules for their SoC designs.
ATPG solution reduces pattern count up to 50%
Synopsys has announced that Toshiba has confirmed that Synopsys TetraMAX II ATPG can significantly accelerate test pattern generation and reduce manufacturing test time and cost. Required to meet aggressive test quality and design schedule goals on an upcoming complex SoC, Toshiba designers determined they would need a much faster ATPG solution that generates much fewer test patterns while being fully power-aware.
Version 8.5 increases static analysis tool's capabilities
Synopsys has announced the version 8.5 release of Coverity, the company's industry-leading static analysis tool and one of the core components of its Software Integrity Platform. Coverity is an automated software testing tool that analyses source code to detect critical security vulnerabilities and defects early in the software development lifecycle.
Development platform adapter accelerates software bring-up
The HAPS adapter that enables a HAPS FPGA-based prototyping system to easily connect to a Juno ARM development platform has been annouced by Synopsys. This software development platform includes the Juno Versatile Express board with ARM Cortex-A72, or Cortex-A57 and Cortex-A53 MPCore, Mali-T624 and reference software through Linaro Linux.
Software delivers superior logic synthesis results
Synopsys has announced a multi-year extension of its OEM agreement with Lattice Semiconductor for Synopsys' Synplify Pro FPGA synthesis tools. With this agreement, Synopsys continues to be the exclusive provider of logic synthesis technology optimised for the highest quality of results, area and runtime for designers targeting Lattice FPGAs and Complex Programmable Logic Devices (CPLDs).
Pulsed latches star as spinner cells for low-power consumption
For integrated circuits with really high volumes, such as MCUs, SESAME uHD (ultra High Density), the flagship product in Dolphin Integration's standard cell library offering, is paramount to decrease die costs. It stars its patented pulsed latches as Spinner Cells instead of standard D-flip flops, openly documented in 'Thorough validation: the conundrum of Pulsed latch libraries turned practical as Spinner systems', which come-up best for low-pow...
Synopsys announces latest RSoft Photonic System Design Suite release
Synopsys has announced the latest release of its RSoft Photonic System Design Suite, the company's software for the design of optical communication systems andPhotonic ICs (PICs) at the signal propagation level. Version 2016.06 introduces a new interface to PhoeniX Software's OptoDesigner chip and mask layout tool to streamline design and fabrication processes for PICs.
Optimised architecture targets high performance applications
An optimised version of the DesignWare PHY and Controller IP Solution for PCI Express (PCIe) 4.0 architecture has been released by Synopses, which reduces latency by up to 20% and area by 15% compared to the previous implementation.