Search results for "TSMC"

At the 2017 International Electron Devices Meeting (IEDM), imec, research and innovation hub in nano-electronics and digital technology, presented the first Power-Performance-Area-Cost (PPAC) analysis of different sequential 3D-integration variants using advanced 5nm and 3nm CMOS technology nodes.

According to Dr. Ana Villamor, Technology & Market Analyst at Yole Développement (Yole): "The GaN market promises an imminent growth. 2015 and 2016 have been undoubtedly exciting years for the GaN power business. we project the explosion of the market with 84% CAGR between 2017 and 2022. The market value will so reach $450m at the end of the period.” What make the power GaN technology so promising?

Cadence Design Systems has announced new capabilities that complete its holistic, integrated design flow for TSMC’s advanced wafer-level Integrated Fan-Out (InFO) packaging technology. Additionally, Cadence has unveiled enhancements for TSMC’s chip-on-wafer-on-substrate (CoWoS) advanced packaging technology. The complete InFO flow and enhanced CoWoS design methodologies enable design teams to efficiently complete the development proce...

Cadence Design Systems has announced that Cadence digital, signoff and custom/analogue tools and flows have achieved v1.0 certification for TSMC’s 12nm FinFET Compact (12FFC) process technology and are production ready for customers seeking to deploy 12FFC. In addition, Cadence IP is ready for design starts on the new 12FFC process.

In order to advance 7nm FinFET Plus design innovation for mobile and high-performance computing (HPC) platforms, Cadence Design Systems has announced its collaboration with TSMC. The Cadence digital, signoff and custom/analogue tools have achieved certification for the latest version of TSMC’s 7nm FinFET Plus process, and Cadence also delivered enhancements to the Cadence library characterisation flow.

A collaboration to build the first Cache Coherent Interconnect for Accelerators (CCIX) test chip with TSMC 7nm FinFET process technology for delivery in 2018 has been announced by Xilinx, Arm, Cadence Design Systems, and TSMC. The test chip aims to provide a silicon proof point to demonstrate the capabilities of CCIX in enabling multi-core high-performance Arm CPUs working via a coherent fabric to off-chip FPGA accelerators.

A comprehensive automotive IP portfolio for the TSMC 16nm FinFET Compact (16FFC) automotive process technology has been delivered by Cadence Design Systems. This broad IP portfolio enables a host of applications ranging from in-vehicle infotainment, in-cabin electronics, vision subsystems, digital noise reduction and advanced driver assistance system (ADAS) subsystems and is registered in the TSMC9000A programme.

IC Insights has revised its outlook for semiconductor industry capital spending and presented its new findings in the August Update to The McClean Report 2017. IC Insights’ latest forecast is for semiconductor industry capital spending to climb 20% this year.

Providing its customers with a complete set of Foundation IPs in TSMC 55nm uLP and uLP eFlash processes, Dolphin Integration have designed these specifically to help reduce the SoC power consumption during sleep and active modes. Lowering the SoC power consumption to support battery-powered devices has always been a challenge for designers.

Customers will be able to accelerate the next-gen of high-performance computing, mobile and automotive products thanks to a new partnership between ANSYSand Synopsys that will tightly integrate ANSYS' power integrity and reliability signoff technologies with Synopsys' physical implementation solution for in-design usage. Developers of innovative, cost-effective and reliable smart products need to quickly optimise, validate and signoff their desig...