Search results for "Synopsys"
Synopsys enters into $100m ASR
In order to repurchase an aggregate of $100m of Synopsys stock,Synopsys has entered into an accelerated share repurchase agreement (ASR) with JPMorgan Chase Bank, National Association. The agreement is in addition to Synopsys' two previous $100m ASRs in 2017 that were settled on 17th May 2017 and 16th February 2017.
Solution enables cache coherency for high performance SoCs
Synopsys has announced the availability of its completeDesignWare CCIX IP solution, consisting of controller, PHY and verification IP delivering data transfer speeds up to 25Gbps and supporting cache coherency for high performance cloud computing applications.
Duo accelerates adoption of advanced security platforms
A new collaboration has been announced betweenRambusand Synopsys to accelerate the adoption of advanced security platforms and technologies to protect valuable assets during key and device provisioning. As part of this collaboration, Rambus will provide its CryptoManager infrastructure and key provisioning services to support Synopsys DesignWare tRoot Hardware Secure Modules (HSMs) with Root of Trust, enabling secure remote lifecycle management o...
Collaboration demonstrates full system interoperability
In order to successfully demonstrate full system interoperability between Synopsys and Mellanox Technologies' two independently developed PCI Express 4.0 solutions, the companies have collaborated together. The demonstration includes a host, which contains the DesignWare Root Port Controller IP for PCI Express 4.0 specification in a DesignWare IP Prototyping Kit, connected to the Mellanox ConnectX-5 network adapter as a device.
FPGA engineering samples offer up to 50% lower power
Provider of semiconductor solutions differentiated by power, security, reliability and performance, Microsemi, has announced its PolarFire field programmable gate array (FPGA) engineering samples (ES) are available for ordering. The PolarFire FPGA family provides the lowest power, cost-optimised mid-range devices spanning from 100K logic elements (LEs) to 500K LEs. Its PolarFire Evaluation Kit, already shipping to key customers, is also available...
Design and verification tools enable successful tape-outs
Early collaboration with ARM on Synopsys' latest IP targeted at artificial intelligence applications, including the ARM Cortex-A75 and Cortex-A55 Central Processing Units (CPUs), the first based on ARM DynamIQ technology, and the ARM Mali-G72 Graphics Processing Unit (GPU), has resulted in successful early adopter tape-outs in advanced FinFET process technologies using Synopsys' Design Platform and Verification Continuum Platform.
Study highlights critical security deficiencies in medical devices
Synopsys has released the results of the study 'Medical Device Security: An Industry Under Attack and Unprepared to Defend',which found that67%of medical device manufacturers and56%of DHOs (Healthcare Delivery Organisations) believe an attack on a medical device built or in use by their organisations is likely to occur over the next 12 months.
Vision Processor improves machine learning applications
Synopsys has announced that it has enhanced the convolutional neural network (CNN) engine in its DesignWareEV6x Vision Processors to address the increasing video resolution and frame rate requirements of high-performance embedded vision applications. The CNN engine delivers up to 4.5 TeraMACs per second when implemented in 16-nanometer (nm) FinFET process technologies under typical conditions, four times more performance than Synopsys' previous C...
Multi-protocol IP reduces power and area by over 35%
Suitable for high-performance computing applications including machine learning and artificial intelligence, Synopsys has announced its new DesignWare Multi-Protocol 25G PHY IP. The PHY IP gives designers the flexibility to efficiently integrate multiple protocols including PCI Express 4.0, 25G Ethernet, SATA and CCIX into system-on-chips (SoCs) targeting the 7 and 16nm FinFET processes.
Parallelism technology reduces regression turnaround time
Synopsys has announced that Acacia Communications has successfully deployed Synopsys VCS Fine-Grained Parallelism (FGP) technology in production, to reduce regression turnaround time (TAT) by two times. With its seamless integration into Acacia's VCS simulation regression environment on existing X86 hardware platform, VCS FGP delivered these simulation performance gains without any changes or disruption to the existing simulation flow.