Search results for "TSMC"

Digital and signoff full flow and custom/analogue tools from Cadence Design Systems have achieved certification on TSMC’s N6 and N5/N5P process technologies. The Cadence tools have attained the latest N6 and N5/N5P Design Rule Manual (DRM) and SPICE certification, advancing next-generation mobile application development.

IC Insights released its ‘August Update’ to the 2019 ‘McClean Report’ earlier this month. This Update included Part one of an in-depth analysis of the foundry industry, an updated forecast for semiconductor capital spending this year, and a ranking of the top-25 1H19 semiconductor suppliers and their 3Q19 sales outlook. The top-15 1H19 semiconductor suppliers are covered in this research bulletin.

Steve Rogerson reports from Taipei on how the country is responding to the moves towards autonomous driving.Taiwan has no major car makers, but the high technology island sees the moves towards autonomous driving and connected transportation as an opportunity that it cannot miss. As such, it is applying the skills it has learned over decades in other electronics sectors to the automotive world in a big way.

It has been announced by Mentor, a Siemens business, that several tools in its Calibre nmPlatform and Analog FastSPICE (AFS) Platform have been certified on TSMC’s 5nm FinFET process technology. Mentor also announced it has successfully completed reference flow materials in support of TSMC’s innovative System-on-Integrated-Chips (TSMC-SoIC) multi-chip 3D stacking technology.

TSMC has certified Cadence Design System’s design solutions for the new TSMC System-on-Integrated-Chips (TSMC-SoIC) 3D advanced chip stacking technology, which integrates heterogenous chips—including logic ICs and memory—that are fabricated on different process nodes onto a single chip stack for a subsequent packaging process.

Good news for Cadence Design Systems is that its LPDDR4/4X memory IP subsystem, utilising TSMC’s 16nm FinFET Compact (16FFC) technology, has achieved ISO 26262 ASIL C certification from SGS-TÜV Saar. The certification confirms that the Cadence IP is complete and ready for use by customers creating advanced systems-on-chip (SoCs) for advanced driver assistance systems (ADAS) and L3/L4 autonomous driving applications.

Avnet Silica has added sister company Avnet ASIC Solutions to its line-up of standard services in EMEA opening the way for customers from SMEs to OEMs to follow a path from design through to manufacture. The business has been built around a 40-strong design team based in Israel and headed by Yulia Milshtein, Director of Operations and Business Development.

Early availability of the complete, silicon-proven Cadence Denali Gen2 IP for LPDDR5/4/4X in TSMC’s 7nm FinFET process technology has been announced by Cadence Design Systems. Offering up to 1.5X faster bandwidth than the fastest speed of LPDDR4 and LPDDR4X, the LPDDR5 standard enables high bandwidth with low power consumption, making it well suited for mobile computing, AI, IoT, cryptocurrency mining and automotive applications.

Today (February 26) at embedded world in Nuremberg, Imagination Technologies and Andes Technology, a specialist in low-power, high-performance 32/64-bit processor IP cores unveiled a collaboration to integrate the new N22 RISC-V MCU IP from Andes with Ensigma low-power IP for Wi-Fi, Bluetooth, IEEE 802.15.4 and GNSS to provide a fully integrated, off-the-shelf solution for the IoT market.

The advancement of the IC industry hinges on the ability of IC manufacturers to continue offering more performance and functionality for the money. As mainstream CMOS processes reach their theoretical, practical, and economic limits, lowering the cost of ICs (on a per-function or per-performance basis) is more critical and challenging than ever.