Search results for "chiplet"

AMD launches Instinct MI200 series accelerators and provides details on expanded set of next-generation EPYC processors at the Accelerated Data Center Premiere.

Advantest Corporation has launched its new Link Scale family of digital channel cards for the V93000 platform, enabling software-based functional testing and USB/PCI Express SCAN testing of advanced semiconductors. The new cards address testing challenges that require these interfaces to run in full protocol mode, adding system-like test capabilities to the V93000.

Semiconductor test equipment supplier Advantest has launched its Link Scale family of digital channel cards for the V93000 platform, enabling software-based functional testing and USB/PCI Express (PCIe) SCAN testing of advanced semiconductors.

Cadence Design Systems has announced that it is expanding its collaboration with Arm to speed hyperscale computing and 5G communications SoC development using Cadence tools and the new Arm Neoverse V1 and Neoverse N2 platforms.

When Rambus was founded 30 years ago, RAM cost $98 per megabyte, and the latest Intel processor, the 80486, had 1.2 million transistors and was fabricated on a 1µm process. In comparison, in September 2020, RAM cost $0.0028 per megabyte, and the latest Nvidia A100 AI processor has 54 billion transistors and is fabricated on a 7nm process. Gary Bronner, Senior Vice President of Rambus Labs, explains more.

Deca has announced the signing of an agreement with ADTEC Engineering to join its new AP Live Network. The partnership allows ADTEC to embed an AP Connect module into its new 2µm Laser Direct Imaging (LDI) system to natively process unique Adaptive Patterning (AP) designs in real-time.

Cadence Design Systems has announced a broad IP collaboration with GLOBALFOUNDRIES (GF) on the 12LP platform and 12LP+ solution encompassing support for advanced memory interfaces including DDR4, DDR5, GDDR6, LPDDR4X and LPDDR5.

A newly enhanced version of ASSET InterTech’s ScanWorks JTAG-based platform of hardware debug, validation and test tools allows engineers to more easily test the device interconnects between silicon ‘chiplets’ in multi-die packages.

Rambus has expanded its portfolio of high-speed interface IP on TSMC’s 7nm process with the addition of its silicon-demonstrated 112G XSR/USR PHY. Offering unmatched power and area efficiency for next-generation applications, the 112G XSR/USR PHY is a critical enabler of chiplet and CPO architectures for data centre, networking, 5G, HPC and AI/ML applications.

With the dawn of the Artificial Intelligence (AI) era upon the world, the usual playbook of continuous shrinking and packing more and more transistors into chipsets will become unsustainable. New AI chip architecture, materials and manufacturing processes will be needed, in order to meet the requirements and realise the potential of the AI-enabled world.