UMC Adopts Synopsys IC Validator for Pattern Matching-Based Lithography Hot-Spot Verification at 28 nm

As part of Synopsys' Galaxy Implementation Platform, IC Validator is an ideal add-on to Synopsys' IC Compiler solution for In-Design physical verification, enabling place-and-route engineers to accelerate time to tapeout by preventing late-stage surprises and minimizing manual fixes. IC Validator pattern matching extends the In-Design flow with automatic repair of lithography violations, further optimizing design turnaround time.

UMC is constantly implementing the latest design support resources to help our customers streamline their path to silicon success, said S.C. Chien, vice president of Advanced Technology Development division at UMC. IC Validator's pattern-matching technology allows our customers to quickly screen for challenging layout features, eliminating the need for detailed process simulation. Furthermore, using IC Compiler and In-Design technology, this checking is available to IC designers earlier in the design process, helping to mitigate risk throughout the design cycle.

Achieving lithographic printability at 28 nm and below can impose significant restrictions on physical design, including large numbers of complex design rule checks (DRC) and compute-intensive detailed process model checking. IC Validator simplifies this task with innovative, patented pattern-matching technology, which augments traditional DRC with intuitive 2D multi-shape pattern-based analysis. Pattern matching enables foundry-quality accuracy and ultra-fast performance, helping to detect lithography hot-spots significantly faster and improve time-to-tapeout.

IC Validator pattern matching extends the benefits of In-Design physical verification with IC Compiler to eliminate late-stage surprises and manual fixes. With pattern matching, designers are now able to screen for lithography hotspots in a push-button manner, right within the implementation environment. Fast pattern-matching analysis utilizes the entire In-Design infrastructure, including intuitive error reporting, GDS merging, error categorization and more. Once detected, violations can be automatically repaired during routing, saving many hours in tedious and error-prone manual fixes. In-Design physical verification with pattern matching makes it possible for designers to reach and maintain a healthy design earlier, resulting in improved final layout quality and further eliminating accumulation of schedule risk.

As complexity continues to grow, it is important that we handle manufacturability as part of design evolution; there is simply no room in tapeout schedules for post-design analysis and manual patching. Our collaboration with UMC on pattern matching is a significant step towards better integration between physical design and verification, said Antun Domic, senior vice president and general manager of Synopsys' Implementation Group. This fully-qualified solution makes it possible for our mutual customers to gain improved visibility into foundry requirements and achieve early tapeouts.