Software release speeds boundary scan project creation

It is now possible to create a single baseline project and then to define how each variant differs from that baseline.

Importing BOM files for each variant allows you to use a wizard that compares the baseline BOM to the imported one and makes proposals on which devices have changed and how to adjust the boundary scan test.

There is also a manual method for use with variants that don’t have their own BOM files.

To run tests in production, test setups containing the necessary data for individual variants can be exported separately, or the variant to be tested can be selected at runtime from a drop-down menu.

Engineers can now bring extra clarity to operator instructions by including images in message boxes and input boxes.

Instead of only using text to describe where to fit a loopback connector, users can now illustrate their guidance with an animation that demonstrates it being fitted, or with a photograph showing it in place.

Repair personnel can also benefit because it enables a way to locate components on the board when an ODB++ netlist isn’t available.

With XJTAG 3.13, tests could be written to display a picture if a board error is found. The image could be of the board with the devices highlighted that are relevant to the detected fault.

The image types supported are JPEG, PNG, GIF (including animated), BMP, and TIFF.

XJTAG 3.13 speeds up the creation of test projects by using a new algorithm that aims to detect when a device you’re working with has an I2C interface. When one is found, all the basic aspects of setting up I2C devices can now be performed automatically.

The detection algorithm works by inspecting the names of nets connected to the device, looking for one containing the text “SCL” and another containing “SDA”.

In addition, if another I2C device has already been set up, the software will check for connections to that device’s bus.

When the test development system recognises that the device uses I2C, it now offers to create a basic test for the device automatically if it doesn’t already have one in its library. The resulting test will check that the device acknowledges its address, and engineers can then build upon that basic test if required by adding their own device-specific tests.

XJTAG’s latest software release also changes how the development system presents results from its attempt to find the circuit’s power and ground nets.

Several different algorithms are still used to identify these nets, but the findings are now combined into a single list, with each identified net given a score to indicate the degree of confidence in the suggestion that it’s power or ground.

The quoted figure is calculated based upon the net’s name, the number of capacitors on the net, and the types of devices connected to it – for example, components that look like inductors or pull-resistors increase the score.

These scores make it easy to find the nets that truly are power, even when they’re not given obvious names. This helps users easily exclude other nets when telling the system which ones to treat as power or ground.