Fast ISP flash configuration delivered for ARM-Based FPGA SoCs

The use of FPGAs with integrated processor sub-systems is increasing. While these sub-systems are fully integrated into the FPGA fabric, they feature their own, dedicated, external non-volatile program memory, connected to the physical pins of the FPGA.

Configuring these memories in both development and production environments is normally a slow and often complex process.

With XJFlash these memories can now be configured simply and at high speed through the JTAG port of the FPGA, without the need for any additional PCB connections. With this latest development, XJFlash is now able to access and configure memory devices connected to a wider range of FPGAs.

This will significantly decrease the time taken to configure on-board memory during development, production and rework. Support for the ARM Cortex-A9 based SoCs extends to partial reconfiguration and optimised erase, delivering further productivity benefits. 

This enables memory devices to be partially erased and reconfigured without having to reprogram the entire device and also minimises the erase time when regions of a device are already blank.

XJFlash forms part of XJTAG’s portfolio of powerful JTAG tools. As well as needing no additional programming hardware, it delivers significantly faster configuration cycles than other programming technologies, for all types of non-volatile memory, including SPI, QSPI and parallel NOR Flash.

XJFlash can be used wherever XJTAG can - as part of a standalone XJTAG test system , or fully integrated into 3rd Party Test Executives (such as LabVIEW) in systems which also use other Automated Test Equipment (ATE).  

Existing licensees will automatically benefit from the expanded capabilities of XJFlash.