Design-for-test platform cuts IC implementation costs

This retrofitting often presents new sets of time-consuming and expensive inefficiencies.

Information has to be carried over manually from one step to the next and if errors are discovered late in the process time to market targets are compromised. And all this work needs a heck of a lot of computing power.

In the next slide Eide, Product Marketing Manager, Design for Test at Mentor, prescribes the DfT aspirin – Tessent Connect, an automation methodology that delivers intent-driven hierarchical test implementation. The headaches are soothed as the tool automatically handles integration, setup and pattern generation. Turnaround times shorten and more reliable and sustainable flows are created.

With Tessent Connect, IC designers interact with the Tessent software design tools using a higher level of abstraction, which describes the intended result rather than step-by-step instructions. The benefits of this abstraction-based approach include seamless collaboration across disparate DFT teams, plug-and-play reuse of IC components, significantly shorter turnaround times and the automation of many time-consuming setup, connectivity and pattern generation tasks.

As part of the Tessent Connect rollout, Mentor has also announced the Tessent Connect Quickstart program, offering detailed flow assessments from Mentor’s applications and consulting services engineers.

An early adopter and beneficiary of Tessent Connect is eSilicon, a provider of FinFET application-specific integrated circuits (ASICs), market-specific IP platforms and advanced 2.5D packaging solutions.

Leveraging the advanced automation of Tessent Connect, eSilicon recently improved IC DFT implementation cost while enabling systemlevel DFT testing and debug capabilities for a highly sophisticated next-generation ASIC.

“eSilicon uses Tessent Connect to help us meet our aggressive production schedules and deliver industry-leading ICs like those based on eSilicon’s neuASIC 7nm platform for machine learning,” said Joseph Reynick, director of DFT services at eSilicon. “As design complexity continues to grow, our system/OEM customers’ needs expand from just focusing on high quality IC manufacturing test to also providing effective in-system test and functional debug capabilities. With today’s complex 2.5D/3D devices, we are not shipping in volume until our chips are fully operational in our customers’ systems, including DFT and IP test. It would be very difficult to meet these challenges without the Tessent DFT portfolio and the efficiencies gained from Tessent Connect automation.”

Mentor is unveiling Tessent Connect at the International Test Conference in Washington (November 12-14).