Sponsored IPs set up at 55nm to reduce SoC power consumption

Dolphin Integration's foundry-sponsored offering of Foundation IPs provide SoC designers with unprecedented capabilities: an instance of 8kx32 of the SpRAM RHEA features a dynamic power consumption as low as 23.14μA/MHz at 0.9V, whilst supporting dual rails to enable data retention at a voltage as low as 0.6V, with minimal leakage. 

The foundry-sponsored Foundation IPs include standard-cell libraries (6T and 9T), a power management kit as well as a complete set of RAM and ROM generators, Sp/Dp/1pRF/2pRF.

Designers leveraging low-power design architectures, such as power gating, dual rail, operations at low voltage, are able to reduce their SoC power consumption by up to 70% compared to LP processes.

Furthermore, the ready-to-use characterisations operating at voltages ranging between 0.9-1.2V allow to reach the targeted SoC frequency with the lowest power consumption. Evaluation kits are provided on request to assess quickly and objectively the achievable performances.

Such standard cell and memory libraries are provided with a complete set of deliverables to achieve the best Time-To-Market. Furthermore, having passed the TSMC IP 9000 Level 4 qualification in both 55nm uLP and 55nm uLPeF, these foundry-sponsored Foundation IPs can be used safely. Other 55nm processes, such as 55nm LP, LP eF and 55nm HV, are also supported.