Dolphin Integration is collaborating with Arm to make embedded and Internet of Things devices more efficient. By combining a set of low-power and high-efficiency voltage regulators with a range of Arm-based IoT System-on-Chip solutions, Dolphin aims to accelerate the cost-effective design of secure, smart and energy-efficient SoCs.

Embedded software development is one of the major focuses to work on in order to reduce time-to-market of microcontroller based products. To this end, the need for a complete and integrated development environment seems to be crucial. 

The THINGS2DO Pilot Line aimed at building a FD-SOI-based European ecosystem fostering innovations for a successful introduction of products onto the market.The project funded and supported the development of major FD SOI-based IPs and ASICs as well as EDA tools.

Dolphin Integration has augmented TSMC’s IP ecosystem at 40nm with TITAN, an architecture for Read Only Memory compiler. This single-layer and late programmable ROM compiler is capable of generating instance sizes from 512bits to 1Mbits. It is available for evaluation on your private space, MyDolphin. This 40nm ULP eFlash ROM compiler, based on the TITAN architecture, combines high-density with ultra-low power consumption.

The challenge of improving the RFID reader detection range and thus the identification rate induce that the chips must be able to operate at extremely low voltage, as the energy caught by the antenna is lowered.

Providing its customers with a complete set of Foundation IPs in TSMC 55nm uLP and uLP eFlash processes, Dolphin Integration have designed these specifically to help reduce the SoC power consumption during sleep and active modes. Lowering the SoC power consumption to support battery-powered devices has always been a challenge for designers.

It requires true differentiating factors when launching any low-power SoC on a highly competitive market. For IoT applications requiring ultra-low-power solutions to extend battery life-time for wireless-connected devices, SoC architects optimise power modes by partitioning the SoC.

Allowing devices to run on the same battery for years rather than months significantly enhances end-user satisfaction. Numerous wireless communication SoC, whether BLE, Zigbee, Sigfox, LoRa or M2M 4G, have a duty cycle such that the power consumption in sleep mode dominates the overall current drawn from the battery.

Although requiring more computing power to run feature rich applications programmes, connected battery-based devices use the minimal energy to ensure the longest usage without recharge. As a result, fabless companies need to hunt down every ‘mA’ to satisfy the low-power expectations of their SoC users.

The industry’s focus on battery-powered devices sets expectations in terms of energy saving for a wide range of applications such as IoT, wearables and wireless MCUs. Meeting the underlying low-power challenge requires a new class of silicon IPs to enable unmatched power consumption figures and new IoT SoC architectures leveraging operating modes with reduced power consumption. In addition, advanced techniques are needed for SoC integration...

Low-power SoCs rely on two design techniques, namely multiple operating frequencies and supply voltages to minimise dynamic power and coarse grain power gating by shutting down parts in sleep mode to save a large amount of leakage power (e.g. up to 99% saving). The implementation of such design techniques requires the insertion of specific cells (power switch cells, isolation cells, level shifters…) at the appropriate places and in th...

Launching any SoC on a highly competitive market demands a differentiation for which Hisense was searching for an ultra low-power solution to extend battery life-time of wireless-connected devices. Designing such an integrated circuit introduces new challenges: silicon area, power consumption and BoM cost must be aggressively reduced, while dealing with noise issues in a mixed-signal SoC embedding multiple power domains with diverse power modes.

For RFID Tags, dynamic power is a critical factor as the capability for lower power translates immediately into a wider range of detection (RFID tag read range) and/or a highest identification rate in the same range. The main degree of freedom to improve power and area of RFID tag is located in the digital block. The SESAME eLC standard cell library enables up to 50% savings of dynamic power when compared to any other logic library available at 1...

Driving the growing demand for voice control is the trend for intuitive and simple user interfaces, either for complementing or for replacing keyboards, touchscreens and other traditional controls.

For integrated circuits with really high volumes, such as MCUs, SESAME uHD (ultra High Density), the flagship product in Dolphin Integration's standard cell library offering, is paramount to decrease die costs. It stars its patented pulsed latches as Spinner Cells instead of standard D-flip flops, openly documented in 'Thorough validation: the conundrum of Pulsed latch libraries turned practical as Spinner systems', which come-up best for low-pow...

Minimising the PCB footprint and the BoM cost implies embedding the Power Regulation Network (PRNet) in the SoC. Meanwhile, minimising drastically the SoC power consumption involves implementing several modes of activity to turn on and off different functions of the SoC, which generates noise on the supply lines during mode switching.

The optimisation of a Power Management Network (PMNet): it is no longer about PMIC or embedded PMU efficiency on Watts, but now, about the waste of energy for the whole SoC in mW for IoT.

Dolphin Integration has rolled-out its new generation of pure logic Audio CODECs, representing a cost effective solution for advanced processes such as 28nm and 16nm. Targeting a silicon area as low as 0.06mm2 at 28nm for the sCODi-N1-DS.01, using SESAME uHD standard cells, a new standard has been achieved for meeting market challenges.

Dolphin Integration has announced the reinforcement of its partnership with imec IC-link for addressing the growing European ASIC market.

For SoCs supplied by Lithium-ion or alkaline batteries, the actual voltage ranges from 4.4V, down to 2.0V over their lifetime. They empower IoT devices, which are often put in sleep mode in order to extend their battery life, requiring ultra-low voltage supplies for their Always-on and retention domains.