SoC optimisation to the next level

Dolphin Integration provides solutions to achieve the lowest power consumption with the smallest silicon area thanks to the noise propagated on supply lines:

A Reduced Power Kit Library (RPKL) compliant with the DELTA Standard, from 180nm down to 28nm, which encompasses various kinds of voltage regulators to meet most SoC requirements:

• eSR-Niagara, a switching regulator providing the best compromise between  power savings (down to 5% of energy waste) and small silicon area.
• qLR-Aubrey, a linear regulator with an ultra-low quiescent current of 150nA including the voltage reference, to supply the Always-on Power Domain.
• Retention Alternating Regulator (RAR), a unique voltage regulator, first of its kind, which ensures the lowest waste of energy in each power mode, both active and retention, of a power island.
• nLR-Charny, an ultra-low noise linear regulator to supply sensitive analog converters or RF loads.
• iLR-Victoria, a linear regulator to supply logic loads or conventional analog loads. It combines small area with fast load transient and fast wake-up time.

DELTA Integration Rules, a set of guidelines ensuring that all constraints are addressed at PRNet level.
Pushing SoC optimisations near the limits and risking to improperly size the PRNet is daunting. Dolphin Integration’s voltage regulators, benefiting from the Delta Integration Rules, allow proceeding with a set of unavoidable verifications when dealing with embedded PRNet, and enable SoC designers to determine necessary but not oversized margins.

To proceed with the needed verifications, Dolphin Integration enables simulating early in the design flows thanks to EDA Solutions.