Imec improves ferroelectric response & endurance of HZO-based ferroelectric capacitors

Researchers obtained this unique combination of properties by interfacial oxide engineering of the ferroelectric capacitor material stack. This high-performance, scalable, CMOS-compatible ferroelectric capacitor technology will be crucial for enabling FeRAM-based embedded and standalone memory applications.

FeRAM is a class of non-volatile memories with the potential to be used as an embedded memory or as a storage class memory (SCM), as such filling the gap between fast DRAM (~10ns access time) and highly dense NAND Flash. FeRAM has a DRAM-like 1-transistor-1-capacitor (1T1C) cell architecture, in which the capacitor’s dielectric is replaced with a ferroelectric material to achieve non-volatility. This ferroelectric material can be in two different polarization states (+P and -P) that can be reversed with an external electric field. For several years, much attention has gone to HZO as a ferroelectric since it is compatible with CMOS processing and scalable below 10nm.

Several characteristics come into play to qualify as an embedded or standalone SCM. Ideally, the capacitor of the FeRAM memory cell has a high endurance (>10¹² switching cycles) in combination with a remnant polarization 2P_R of 30-40µC/cm² during the entire lifetime. So far, such a combination has never been reported because the capacitors suffer from either a prolonged wake-up (small 2P_R in the beginning) or fast fatigue (rapidly degrading 2P_R).

“By interfacial oxide engineering, adding both a 1nm TiO₂ seed layer and 2nm Nb₂O₅ cap layer to the La:HZO layer, we achieved for the first time high endurance (10¹¹ cycles) in combination with a final 2P_R as high as ~30µC/cm² (at an applied electric field of 1.8MV/cm) and good initial 2P_R,” explains Jan Van Houdt, program director of ferroelectrics and fellow at imec. “Following an initial understanding, contact with the Nb₂O₅ capping facilitates the transition to the desired orthorhombic phase of HZO (i.e., the ferroelectric phase) by injecting oxygen into the HZO layer, while the TiO₂ layer favors the preferred (002) grain orientation further resulting in a higher initial 2P_R.” Alternatively, using a different precursor for depositing the HZO layer, a record-high 2P_R of 66.5µC/cm² at 3MV/cm was obtained, though with an endurance of 10⁶ cycles.

“Now we have a high-performance, scalable, and CMOS-compatible ferroelectric capacitor technology that will bring us to the next exciting phase, i.e., moving from planar to 3D FeRAM capacitor structures – leveraging atomic layer deposition (ALD) processes,” added Jan Van Houdt. “This will increase the density needed to bring FeRAM memories to the market as a new embedded or standalone memory.”