Read only memory helps augment TSMC IP ecosystem

11th April 2018

Enaie Azambuja

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Dolphin Integration has augmented TSMC’s IP ecosystem at 40nm with TITAN, an architecture for Read Only Memory compiler. This single-layer and late programmable ROM compiler is capable of generating instance sizes from 512bits to 1Mbits. It is available for evaluation on your private space, MyDolphin. This 40nm ULP eFlash ROM compiler, based on the TITAN architecture, combines high-density with ultra-low power consumption.

This architecture has already been silicon proven in 55nm and 90nm process technologies. The TITAN ROM compiler reduces fabrication costs and time-to-market as programming is performed using only the metal 1 layer.

Configurable multiplexer option, from 8 to 128, provides designers with the flexibility to select a ROM configuration to meet the target performances with the optimal floorplan. The online ROM compiler allows the designer to quickly complete an objective performance assessment. It automatically generates datasheets, simulation (Verilog), layout (GDSII), footprint (LEF), timing/power (Liberty) and MBIST (Tessent) models.“

“There are a number of applications which still embed a large amount of ROMs to store the application program, be it Low Energy Bluetooth, BT audio, etc.,” said Frédéric Masson, Business Unit Manager at Dolphin Integration.

“The density of our sROMet, which is known for enabling up to 35% area savings, partakes in ensuring the best competitive advantage in such cost-sensitive applications!”

To enable the cost-effective design of energy-efficient SoCs, Dolphin Integration is expanding its portfolio of foundation IPs at TSMC 40nm to complement their existing offering of Power Fabric IPs.

Complementary to this ROM compiler, a new generation of dense and low-power SRAM memory compilers (Single-port RAM TELESTO and Dual-port RAM ERA) is under completion as well as a standard-cell library (SESAME BiV) dedicated to always-on power domains.