Portfolio of advanced memory and SerDes PHYs on TSMC N7 process

As the fastest discrete memory interface from Rambus, GDDR6 memory PHY adds to TSMC’s most comprehensive portfolio of silicon-proven intellectual property (IP), design tools and Reference Flows through the TSMC IP Alliance Program, a key component of TSMC Open Innovation Platform (OIP). Along with HBM2 and 112G LR SerDes PHY, Rambus offers leading-edge memory and serial link interfaces for a broad range of high-performance applications.

“TSMC OIP Alliance partners continue to deliver innovative solutions that will address the tremendous demands for computing power driven by AI and next-generation networks,” said Suk Lee, TSMC Senior Director, Design Infrastructure Management Division. “We’re pleased with the availability of Rambus’ high-speed memory and SerDes interface solutions on TSMC’s industry-leading N7 process technology to address customer’s requirements for the most demanding applications.”

Expanding beyond the traditional GPU and graphics applications, GDDR6 and HBM2 address market needs in multiple, advanced applications like AI/ML, ADAS and networking, as memory bandwidth becomes more critical for overall system performance. As the industry rapidly transitions to 400 and 800GbE communications systems, 112G LR is a key building block necessary to support the ever-growing demand for more bandwidth in data centre and network applications.

“This announcement highlights Rambus’ leadership in high-speed SerDes and memory PHY IP, leveraging the company’s long tradition of signal- and power-integrity expertise,” added Hemant Dhulla, Vice President and General Manager of IP cores at Rambus. “We are very proud to be able to offer these advanced solutions as part of the TSMC ecosystem.”

The Rambus GDDR6 and HBM2 Memory PHYs, and 112G LR SerDes PHY are available from Rambus today for licensing and integrating into system-on-chip (SoC) designs.