Rambus has announced the availability of its DDR5 Client Clock Driver (CKD) for next-generation, high-performance desktops and notebooks.

As the automotive industry leans towards software-enabled autonomous, connected, and electric vehicles, cyber security is emerging as a new benchmark of quality.

Available now from Rambus is its Gen4 DDR5 Registering Clock Driver (RCD) that began sampling to the major DDR5 memory module (RDIMM) manufacturers in the fourth quarter of 2023.

Rambus, a premier chip and silicon IP provider making data faster and safer, has announced a full suite of Security IP solutions for the FPGA market with state-of-the-art cryptographic, side-channel, and Quantum Safe protections.

Paige West talks with Neeraj Paliwal, GM of Security IP at Rambus about autonomous vehicles and security.

When Rambus was founded 30 years ago, RAM cost $98 per megabyte, and the latest Intel processor, the 80486, had 1.2 million transistors and was fabricated on a 1µm process. In comparison, in September 2020, RAM cost $0.0028 per megabyte, and the latest Nvidia A100 AI processor has 54 billion transistors and is fabricated on a 7nm process. Gary Bronner, Senior Vice President of Rambus Labs, explains more.

Rambus has announced the availability of a high-performance IPsec Packet Engine with integrated DPDK and companion key negotiation toolkit capable of securing 5G network traffic at data rates from one to 10Gbps. A complete IPsec solution, the packet engine can be easily integrated into SoCs for a broad range of 5G devices from base stations and cloud, to gateways and end devices.

Rambus has announced it has achieved a 4Gbps performance with the Rambus HBM2E memory interface solution consisting of a fully-integrated PHY and controller. Paired with the industry’s fastest HBM2E DRAM from SK hynix operating at 3.6 Gbps, the solution can deliver 460 GB/s of bandwidth from a single HBM2E device.

The top six most significant specification advances made in the transition from DDR4 to DDR5 DIMMs are shown in Table 1 below.

Changes in DDR5 have introduced a number of design considerations dealing with higher speeds and lower voltages – raising a new round of signal integrity challenges. Designers will need to ensure that motherboards and DIMMs can handle the higher signal speeds. When performing system-level simulations, signal integrity at all DRAM locations need to be checked.

Rambus has expanded its portfolio of high-speed interface IP on TSMC’s 7nm process with the addition of its silicon-demonstrated 112G XSR/USR PHY. Offering unmatched power and area efficiency for next-generation applications, the 112G XSR/USR PHY is a critical enabler of chiplet and CPO architectures for data centre, networking, 5G, HPC and AI/ML applications.

Rambus has announced the CryptoManager Root of Trust RT-640 and RT-645 cores have been certified ASIL-B and ASIL-D ready, respectively. These automotive-grade secure co-processor IP safeguards SoCs in V2X communications, ADAS, ECU platform management, infotainment and other critical vehicle systems.

Driver assistance systems such as cruise control are now part of the standard specification in a modern vehicle. ADAS Level-2 (L2), partial automation, and the first Level-3 (L3) conditional automation systems are in the market, but the journey to full automation still has some years to go. Here, Frank Ferro, Senior Director of Product Marketing for IP cores at Rambus explains.

Rambus has announced its 800G MACsec (Media Access Control security) solution for next-generation networking infrastructure. The 800G MACsec solution delivers hardware-based, point-to-point security for 800 Gigabit Ethernet links and is a critical element of end-to-end network security.

Rambus has announced a comprehensive interface solution for HBM2E memory consisting of co-verified PHY and memory controller. Operating at a top speed of 3.2 Gbps over a 1024-bit wide interface, the interface can deliver 410 GB/s of bandwidth with a single HBM2E DRAM stack.

Rambus has announced that Enflame (Suiyuan) Technology has selected Rambus HBM2 PHY and Memory Controller IP for its next-generation AI training chip. Rambus memory interface IP enables the development of high-performance, next-generation hardware for leading-edge AI applications.

Rambus has announced a broad portfolio of high-speed memory and SerDes PHYs for next-generation applications on TSMC’s industry-leading N7 process technology. Rambus offers GDDR6, HBM2 and 112G LR PHY IP available for licensing, these solutions enable demanding applications for data centre, networking, wireless 5G, HPC, ADAS, AI and ML.

Steven Woo of Rambus explains some of the challenges to closing the AI memory gap. Over the last 15 years the use of artificial intelligence (AI) techniques has boomed. We now carry AI assistants in our pockets, trust algorithms to provide image recognition in autonomous vehicles and use machine learning to predict the spread of disease. The development of these modern AI applications has only come about because of advances in AI algorithms,...

Rambus has announced the tapeout of its 112G XSR SerDes PHY on a 7nm process node optimised for PPA. As the industry continues to adopt chiplet architectures for networking and compute applications, the Rambus 112G XSR SerDes PHY represents the latest advancement in high-speed signalling technology for die-to-die (D2D) and die-to-optical engine (D2OE) connections.

Scott Best, Technical Director of Anti-Counterfeiting Products, Rambus, explains the role of cryptographic ICs. As system counterfeiting attacks continue to send shockwaves across industries, design engineers are evaluating how best to deploy cryptographic authentication integrated circuits (ICs) to secure systems. While there is no shortage of options available, in reality many of these solutions provide very poor levels of additional secur...