Processor core eases integration of IoT devices

The core, which is the first of the company's offerings to use the v2 instruction set, is targeted at low power always on/always listening systems. Systems with less demanding clock frequencies such as Bluetooth Smart are also targeted. Offered in Harvard architecture, the processor core features sixteen 32-bit registers, a 3-stage pipeline and a sequential multiplier. The AXI4-Lite bus and Cortus APS peripherals are supported by the core. In computational performance, the processor core delivers 2.83DMIPS/MHz and 1.44CoreMarks/MHz. When optimised for area, the core starts around 9.8kgates. The synthesisable and foundry independent core provides 12µW/MHz dynamic power with a 90nm process.

The mixing of 16, 24 and 32-bit instructions without mode switching is enabled by the v2 instruction set. Cortus will continue to offer products based on the v1 instruction set, which uses a mix of 16 and 32-bit instructions. All C/C++ or assembler code developed for the v1 cores can be used unmodified on the v2 cores.

Via the APS bus, the processor core can interface to Cortus’ Ethernet 10/100 MAC, USB 2.0 Device and USB 2.0 OTG peripherals. To ensure rapid, real time interrupt response with low software overhead, both the core and peripherals share the same vectored interrupt structure. The APS tool chain and IDE (for C and C++), which can be customised, is available to licensees free of charge.

“The IoT and other smart devices are rewriting the rules for developing systems-on-chip and fuelling huge growth for the semiconductor industry,” said Rich Wawrzyniak, Senior Analyst for ASIC & SoC, Semico Research. “[The] IoT is creating a massive universe of connected intelligent devices that place stringent demands on processor IP and potentially represent much bigger unit numbers than the mobile market. What’s needed is a minimalist approach to power, silicon area and cost without sacrificing performance or security. This is what Cortus is doing and why Semico believes the company is well-positioned to meet the needs of this emerging market.”

“Cortus cores have a proven track record in low power applications such as wireless, smart sensors and touchscreen controllers,” said Mr. Michael Chapman, CEO and President, Cortus, “However we know that today’s smart applications require a new generation of IP - IP designed with a minimalistic approach to system silicon area and power consumption while also providing good cost of ownership and key functionality. We have focused on reducing the size of the instruction memory which is usually the largest single component in a system and are seeing an average 16% improvement in code density over our earlier (v1) cores.”