As part of the Cortus IC Design Service offering, Cortus has announced the general availability of a complete range of RISC-V processors. These are now available for design-in in customer ASIC designs implemented by the experienced teams at Cortus.

  XTERCONNECT and GENIATECH having already developed a range of professional industrial IoT solutions using LoRa technology have entered into a strategic and industrial partnership with CORTUS to develop and deliver a range of secure products and solutions for IoT using its CIoT25 low power IoT platform based on Dash7 technology.

The SIPO IoT Forum, taking place on 20th June 2017 and the NKIC Seminar at Nan-Kang Incubation Center on the 22nd June 2017, both taking place in Taipei, Taiwan, will see Cortus present the ‘Challenges in ASIC Design for IoT’.

Cortus has announced that they will be presenting 'Challenges in ASIC Design for IoT' at the IoT seminar. They will complement this with a seminar later in the week covering a number of these aspects in greater detail.

A high performance, dual issue version of Cortus' APS25 IP core has been released. The APS29 is the fourth in a family of products based on the Cortus v2 instruction set. The core is aimed at embedded systems requiring good computational performance while also delivering efficient silicon area and modest power dissipation.

Cortus has announced its relationship with Angstrem-T. As a result of this work, the leading Russian semiconductor Foundry Angstrem-T has developed an ASIC based on a Cortus APS 32-bit microcontroller core. Cortus licenses a range of low power, 32-bit processor cores for smart devices including IoT, smart cards, smart sensors & industrial control. The APS range of processors are all modern, advanced 32-bit RISC processors, with out-of-order c...

Cortus and Aspen Logic announce an educational webinar on creating ASICs for IoT & M2M products. The presentation entitled 'Attention IoT Developers: Yes, your Things can stand out!' will run live at 10:00a.m. PST/ 6:00 p.m. GMT on 16th February 2016.

Synic Solution and Cortus announced that the Synic SKY5000 integrated Dual Card Reader solution uses a Cortus APS23 core to enable the flexible implementation of user applications. The Synic SKY5000 is fully compliant with the EMV4.1 standard for secure payment transactions and the ISO-7816 standard for smartcards with contacts and supports Class A/B/C supplies with an external 5V power input.

Cortus announced the release of the FPS26 single precision floating point IP core, the third in a family of products based on the Cortus v2 instruction set. The core is aimed at embedded systems requiring good floating point computational performance while also delivering small silicon area and low power dissipation.

Work between Cellnetrix and Cortus has led to the CellSIM secure embedded operating system being available for Cortus 32-bit APS processor IP cores. CellSIM, already widely deployed in securing SIM/USIMs for telecommunications, will enable the developers of systems-on-chip (SoCs) for IoT and M2M to secure their communication protocols and to securely update their firmware over the network.

Cortus has announced the availability of a development platform for its APS processor cores. The Cortus development platform comprises a board based on a Xilinx Spartan-6X75, the Cortus Eclipse IDE and the Cortus GCC toolchain. The board includes an I/O footprint compatible with the Arduino Due, enabling the wide choice of Arduino Due-compatible shields to be used to extend the platform.

Cortus and Nabto have announced the availability of the uNabto communication platform on Cortus’ APS processor cores. uNabto is a low-bandwidth web server protocol that runs on any Cortus APS core and employs an innovative approach to bypassing firewalls and providing GUI-based internet access to a wide range of embedded applications, using only 16KB of Flash and less than 1kB of RAM. uNabto running on Cortus APS cores with the Cortus Ether...

Oryx Embedded's CycloneTCP, a dual IPv4 & IPv6 stack aimed at embedded applications, is now available on Cortus’ APS processor cores. By supporting IPv6, the stack enables the development of SoC for both IoT edge devices and complex gateways.

Blunk’s CrossStep IDE and TargetOS RTOS are now available for Cortus’ APS processor cores. The CrossStep is an Eclipse alternative for embedded developers that includes a high-level source debugger GUI, a project manager/builder and integrated kernel awareness. The IDE supports JTAG debug interfaces, as well as debug-over-Ethernet connections via Blunk’s advanced debug monitor. The device is an IDE that uses the GNU gcc and gdb.

Designed for low-power, connected intelligent devices, the APS23 processor core has been introduced by Cortus. Based on the company's v2 instruction set, the core improves efficiency, eases integration and lowers the total cost of ownership. The v2 instruction set reduces the size of the system's instruction memory, allowing the processor core to reduce embedded system power.

Cortus and IMAGIS have announced that they are working together to develop touchscreen designs based on Cortus' APS1 processor core. This 32-bit processor core has been designed to replace the 8-bit microcontroller core, with Cortus claiming it saves silicon area and reduces code size, making it more cost effective. The APS1, which has 64kB of program and data memory, features Ethernet 10/100 MAC, USB 2.0 and USB 2.0 OTG interfaces.

Cortus, the low power processor IP company, has joined the Global Semiconductor Alliance (GSA), the voice of the semiconductor industry.

In a range of high performance image sensor designs, Pyxalis has used Cortus processor subsystems for a high level of software integration dedicated to sensor operation management. The processors offer the possibility to integrate more application-specific image processing functions such as auto-white balance, auto-exposure control, etc.

Securing smartcards below the OS is necessary to provide cards with a high degree of tamper-resistance. Therefore, Cortus and Secure-IC are collaborating in providing low power secure solutions for smartcard developers. By offering security solutions tailored to a particular customer’s requirements, a good trade-off can be made between the degree of protection and the cost in silicon.

Cortus announce the opening of a new office in Silicon Valley and the appointment of Jack Dean to head up applications engineering in the Americas. A graduate of California State University, Mr Dean, brings extensive technical experience in the development of hardware and software for embedded systems and SoCs.