FPGA simulation IDE adds VHDL-2019 support

Support has also been added for release 2020.08 of the open source VHDL verification methodology (OSVVM).

Active-HDL is an integrated design environment (IDE) that includes a full HDL and graphical design tool suite plus an RTL / gate-level simulator for the rapid deployment and verification of FPGAs. These features, combined with the latest revisions to VHDL, empower engineers to create, maintain, re-use and easily verify their designs.

“VHDL-2019 was requested by users, ranked by users, scrutinised by users, written by users, and balloted by the VHDL community,” commented Jim Lewis Director of VHDL Training at SynthWorks and IEEE 1076 VHDL Working Group Chair. “Just as they were for VHDL-2008, Aldec is at the forefront of implementing the new language features. This is good news as the VHDL verification community is ready to start using VHDL-2019."

Support for OSVVM 2020.08 gives users of Active-HDL access to the free and open-source methodology’s new requirements tracking, updated scripting, AXI4 full verification components, and model independent transactions.

Sunil Sahoo, Aldec’s SW Product Manager, added: “We’re committed to the VHDL user community from an EDA tools perspective as well as supporting all methodologies that aim to boost productivity and give engineers confidence in their designs.”

The latest version of Active-HDL also sees SystemVerilog enhancements that include initial support for multidimensional arrays of instances, preliminary support of unresolved user-defined nettypes, and preliminary support for unique constraints.

Several non-standard extensions to SystemVerilog are present in the latest release of Active-HDL too. These include allowing variable type outputs of clocking blocks to be driven by a continuous assignment, allowing the use of foreach loops iterating over the elements of a subarray, and assigning a virtual interface with a modport to a virtual interface without a modport.