Aldec, Inc. has unveiled the latest release of Riviera-PRO, providing support for system simulation of Versal Adaptive Compute Acceleration Platform (ACAP) designs.

Aldec, Inc., specialists in mixed HDL language simulation and hardware-assisted verification for FPGA and SoC designs, is supporting Open Component Portability Infrastructure (OpenCPI) with the latest release of Riviera-PRO (release version 2022.04).

Aldec has launched HES-DVM Proto Cloud Edition (CE). Available through Amazon Web Service (AWS), HES-DVM Proto CE can be used for FPGA-based prototyping of SoC / ASIC designs and has a focus on automated design partitioning to greatly reduce bring-up time when up to four FPGAs are needed to accommodate a design.

Aldec has enhanced Active-HDL to support new features within VHDL-2019 (IEEE 1076-2019). These features simplify the language, lift certain restrictions that were present in earlier versions and introduce new application programming interfaces (APIs).

Aldec has added PYNQ Python Productivity for Zynq from Xilinx to its TySOM family of Xilinx Zynq SoC based boards and its TySOM Embedded Development Kit. The Xilinx PYNQ framework (pronounced ‘pink’) is the popular open source platform that is enabling software engineers to develop applications for Xilinx SoC and MPSoC devices with reduced reliance on support from hardware engineers.

Aldec has enhanced its unified requirements lifecycle management EDA tool, Spec-TRACER, to support the exchange of system and hardware data with IBM Requirements Engineering DOORS Next product, commonly used by system engineers.

Aldec has added features to its Riviera-PRO functional verification platform that provide further support when working with the latest version of VHDL (2018) as well as the 2019.09.02 release of the Universal VHDL Verification Methodology (UVVM).

Aldec has launched a powerful, versatile and time-saving FPGA-based NVMe Data Storage solution to aid in the development of High Performance Computing (HPC) applications such as High Frequency Trading and Machine Learning.

Aldec has introduced automatic FPGA partitioning to its popular HES-DVM; the company’s fully automated and scalable hybrid verification environment for SoC and ASIC designs. Traditionally, the manual partitioning of multiple FPGAs used for prototyping can take days, or even weeks, whereas the automation in HES-DVM can perform the task in minutes; ideal for exploratory, What-If scenarios.

  Aldec has launched the TySOM-3A-ZU19EG, to assist in the development of AI, Deep-learning Neural Network (DNN) and other applications dependent on complex algorithm acceleration in firmware.

Aldec is making available yet more support for automotive design engineers with the addition of an Advanced Driver-Assistance System (ADAS) ‘Bird’s Eye View’ reference design for its TySOM-3-ZU7EV embedded development kit.

  Electronic design verification company, Aldec, has expanded the rule-checking capabilities of its ALINT-PRO tool in response to growing complexity of large-scale modern FPGA and ASIC designs. Rules new to the 2017.12 release of ALINT-PRO assure the integrity of a design’s Finite State Machines (FSMs) and help identify possible Reset Domain Crossing (RDC) issues.

Aldec announces the latest release of its mixed-language advanced verification platform, Riviera-PRO 2013.02. This release includes numerous enhancements, including visual debugging tools that improve the presentation of simulation results for increased overall verification efficiency.

Aldec today unveiled Fast Track ONLINE, a convenient, online training portal that is available at no cost to the design verification community. In today’s competitive atmosphere, the ability to adopt new technology quickly and reduce design time cycles is critical.

Aldec, Inc., in collaboration with SynthWorks Design Inc., today announces the availability of Open Source - VHDL Verification Methodology (OS-VVM™), underscoring the partnership’s commitment to provide continued support to the VHDL design community.

Aldec, Inc. has announced the availability of the RTAX-S Prototyping Board for radiation-tolerant RTAX-S FPGAs from Actel Corporation (NASDAQ:ACTL). Easing the prototyping process of space-flight systems, the new RTAX-S Prototyping Board provides the flexibility Actel's flash-based ProASIC3 FPGAs offer, allowing designers to utilize a design across multiple aerospace projects, shorten design cycles and lower project costs. Together with automati...

Aldec has announced the release of co-simulation support for fixed-point in Simulink. Active-HDL coupled with The MathWorks Simulink provides support for fixed-point types and HDL co-simulation of black-boxes, which allows seamless integration with Simulink-based DSP tools.

Aldec, Inc has announced System Verification Environment (SVE) support for Altera Corporation's new high-end Stratix III FPGA device family. SVE supports all aspects of system-level design development and verification. It includes an industry-leading common kernel HDL simulator, a set of on-line debuggers, code coverage, cross-probing tools and an industry-first integrated simulator server farm manager (SFM) for automatic verification of ultra-...

Aldec, Inc. has announced the addition of Expression Coverage for Verilog in the release of Riviera 2006.06. This addition significantly improves efficiency of the verification process and enables delivery of higher quality, more reliable designs.

Aldec has announced that its simulator now has integrated HDL support from Altera's Quartus II version 6.0 development software environment. Mutual customers can now select Aldec's HDL Simulator, Active-HDLT, directly from Altera's Quartus II software version 6.0.