Building on the established PP10 platform, this advanced technology features WIN’s second-generation humidity resistance process, EMRII, which provides mechanical protection and moisture ruggedness at the wafer level.
The EMRII layers form localised air cavities over all transistors, minimising added parasitic capacitance and ensuring moisture resistance with minimal impact on gain, noise figure, and output power. This feature mitigates amplifier performance changes due to packaging, plastic encapsulation, or PCB embedding, thus speeding up new product development.
At the core of PP10-29 is a versatile 0.1µm-gate D-mode with ft/fmax of 145GHz and 180GHz respectively, qualified for 4V operation. Manufactured on 150mm GaAs substrates, this platform offers two interconnect metal layers, air-bridge crossovers, precision TaN resistors, monolithic PN-junction diodes for compact on-chip ESD protection circuits, and through-wafer vias for low-inductance grounding. PP10-29 supports various DC and RF I/O configurations, including standard wire-bonding, frontside Cu-bumps/RDL, and through-chip RF and DC transitions, providing a path to new packaging and assembly options.
PP10-29 has reached beta release and is available for early access MPW runs. Qualification testing is complete, and final modelling/PDK generation is expected to conclude in August 2024, with full production release scheduled for late Q3 2024. Contact a WIN Semiconductors regional sales manager for information about sample kits and the timing of MPW runs.
