VIP for PCI Express architecture supports M-PCIe technology

The VIP for M-PCIe is integrated with the company's Verdi Protocol Analyzer, a protocol-aware environment that speeds debug by providing simplified views of protocol traffic. The introduction of the VIP expands the company's verification IP portfolio for PCIe, which supports all versions of the PCIe technology and NVMe. The complete M-PCIe IP solution consists of verification IP, a silicon-proven DesignWare M-PCIe digital controller and M-PHY which enables project teams to accelerate development of M-PCIe-based SoCs and hit critical market windows.

"As an active PCI-SIG member, Synopsys has been a valued contributor to the advancement of PCIe technology," said Al Yanes, PCI-SIG chairman and president. "The Synopsys VIP support for the M-PCIe architecture further helps the PCI Express ecosystem attain adoption within an increasing range of platforms."

"The release of new protocol versions to address new market segments creates a complex and lengthy ramp-up process for design teams as they strive to rapidly verify compliance against the new specification," said Debashis Chowdhury, vice president of R&D for the Synopsys Verification Group.  "We continue to deliver VIP for new versions of protocols to enable our customers to achieve their SoC verification closure goals and accelerate time-to-market.  The new Synopsys' VIP for M-PCIe protocol provides designers with the built-in protocol knowledge, features and methodology support to save time, increase design quality and meet project schedules."

Visitors to he MIPI Alliance All Members Meeting in Shanghai, taking place October 6th - 10th 2014, will be able to see a demonstration of the VIP for M-PCIe. The VIP for M-PCIe is available today for early adopters as a stand-alone title and as part of Synopsys' Verification IP Library, including the Verification Compiler. The DesignWare M-PCIe digital controller and PHY are available now.