Verification tool shortens time-to-market for advanced SoCs

Synopsys has claimed that the Verification Continuum platform is built from the industry's fastest verification engines including Virtualizer virtual prototyping, Verification Compiler static and formal technologies, VCS simulation, ZeBu emulation, HAPS FPGA-based prototyping and Verdi³ debug. This provides the capacity and performance required to verify many of the world's largest and most complex chips.

Verification Continuum includes Unified Compile with VCS across the verification flow. This enables a robust simulation-like user experience that engineers can use to transition between simulation, static and formal verification, emulation, FPGA-based prototyping and debug. Unified Compile with VCS eliminates the need for extensive setup and move a design between different tools, saving months in typical project schedules.

The verification platform also features Unified Debug based on Synopsys' Verdi³ environment, offering a consistent debug experience for higher productivity. Verdi³ offers a single interface for multi-domain debug across virtual prototyping, static and formal verification, simulation, emulation and FPGA-based prototyping. It also enables fully synchronised, mixed-abstraction debug between SPICE, RTL, transactions and software.

By seamlessly integrating FPGA-based emulation and prototyping into mainstream verification flows, Verification Continuum has been architected to support FPGA-based verification platforms. Saving significant design time, the platform delivers up to three times faster compile time for Synopsys' ZeBu Server-3 emulation system.

Victor Peng, Executive Vice President and General Manager, Programmable Products Group, Xilinx, comments: "The Verification Continuum requires an optimised software flow combined with the highest-performance, highest-capacity emulation and prototyping hardware. Xilinx has raised the bar again with our Virtex UltraScale devices, offering the largest 20nm FPGA in the industry, the XCVU440. We are working closely with Synopsys to optimise our Vivado Design Suite flow to address the unique requirements of hardware-assisted verification users."

Synopsys' Verification Continuum is scheduled for early availability in December 2014, with general availability in 2015.