Verific Design Automation Adds Features to UPF Parser for Enhanced Support of IEEE Standard

Newly introduced UPF 2.1 features are supported in the UPF parser. It performs syntax and semantic checking, preserves all parameter values and stores the UPF data in a parse tree for easy access. The UPF parser includes Verific’s comprehensive error handler, which maintains complete file, line and column information on UPF descriptions.

An integral component of Verific’s Parser Platform, the UPF parser interacts seamlessly with Verific’s standard SystemVerilog and VHDL parsers. It queries parse trees or netlists where applicable or, conversely, can be queried from Verific’s SystemVerilog or VHDL parse trees, or its netlist database. The UPF parser is also available standalone and is easily integrated with external, or non-Verific, data structures.

The IEEE 1801-2013 UPF 2.1 standard, originally developed by standards organization Accellera, is supported by multiple electronic design automation (EDA) vendors, many of whom are Verific customers. It provides a hardware description language independent way of annotating a design with power intent. It defines how to create supply networks to supply power to each design element using a set of commands.

“In a short period, UPF has become an important standard for describing low-power design and support is a priority for us,” remarks Michiel Ligthart, Verific’s president and chief operating officer.

Verific’s software is the front end to a variety of EDA and field programmable gate array (FPGA) tools for analysis, simulation, verification, synthesis, emulation and test of register transfer level (RTL) designs. Its Parser Platform includes support for SystemVerilog, Verilog, VHDL and UPF, and provides C++ and Perl application programming interfaces (APIs). Verific’s software is distributed as C++ source code and compiles on all 32- and 64-bit Unix, Linux and Windows operating systems.

Verific to Exhibit at DVCon

Verific will exhibit in Booth #805 during DVCon Monday, March 3, from 5 p.m. until 7 p.m., and Tuesday and Wednesday, March 4-5, from 2:30 p.m. until 6 p.m. DVCon will be held at the DoubleTree Hotel in San Jose, Calif.