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Verific Design Automation
- 1516 Oak Street
Suite 115 Alameda
Calif. 94501
United States of America - +1 510 522-1555
- http://www.verific.com.
Verific Design Automation Articles
Displaying 1 - 2 of 2
Design
19th June 2014
Invionics Unveils VRDM Development Platform for Rapid Deployment of Verific HDL Parsers
Invionics took the wraps off the VRDM Development Platform that layers a rapid development interface on top of Verific’s industry-standard, IEEE-compliant SystemVerilog and VHDL parsers.
Design
12th February 2014
Verific Design Automation Adds Features to UPF Parser for Enhanced Support of IEEE Standard
Verific Design Automation announced enhancements to its parser for the IEEE 1801-2013 standard for the design and verification of low-power integrated circuits, also known as Universal Power Format 2.1 (UPF 2.1).