TSMC selects Synopsys HSIM Simulator for sub-40nm memory IP characterisation

“At 40nm nodes and beyond, post-layout parasitic data, power reliability and leakage need to be accounted for when characterising memories,” said ST Juang, senior director of Design Infrastructure Marketing at TSMC. “We had adopted HSIM for our memory IP characterisation at previous technology nodes, and after extensive evaluation we chose HSIM for our sub-40nm flow based on its advanced technologies for post-layout analysis and its ability to deliver accurate simulation results while maintaining fast throughput for our largest memory compilers.”

As layout geometries shrink, accurate characterisation of memories becomes more of a challenge. Previous methodologies that have employed critical path and cut netlists are no longer adequate to accurately verify the impact of cross-coupling effects and layout parasitics. As a result, more customers have adopted the method of verifying the entire memory design, including the chip packaging, for sub-40nm process nodes. HSIM, the technology-leading FastSPICE circuit simulator, addresses this challenge by delivering accurate simulation results with superior performance. HSIM provides a comprehensive solution for circuit simulation, post-layout analysis, reliability analysis and electrical rule checking.

“TSMC’s selection of HSIM for their most advanced memory IP characterisation validates our continued R&D investment in circuit simulation technologies,” said Paul Lo, senior vice president and general manager of the Analog/Mixed-Signal Group at Synopsys. “Through collaboration with companies like TSMC, we are able to deliver solutions for our customers’ toughest circuit verification challenges.”