Tensilica Offers Integrated Real-Time Trace Support to Xtensa Configurable and Diamond Standard Processor Cores

Tensilica has been finding new interest in its processors in two areas involving real-time control. First, for standard control processors, the Diamond Standard processor family includes low-power, efficient 32-bit controllers. Particularly, the recently introduced Diamond Standard 106Micro, the smallest licensable 32-bit core, is very attractive to designers moving up from 8- and 16-bit controllers in these applications.

Second, Tensilica's Xtensa configurable processors can be exactly configured and matched to the application. In many real-time applications, adding instructions to the processor that accelerate data processing can enable meeting the real-time constraints in a much more area and power efficient way versus traditional approaches of increasing the frequency (MHz) of the processor. This can allow a much smaller, lower-power, optimized Xtensa processor to replace a much bigger general-purpose processor core.

Difficult debugging problems are sometimes caused by subtle interactions between subsystems and other timing consideration in hard real-time systems. State-of-the-art processor trace tools can ease system integration, solidify product schedules and accelerate revenues, stated Chris Rowen, Tensilica's president and CEO. By adding trace capability, designers can feel confident in their ability to debug and deploy FPGA prototypes or SOC silicon solutions.

Tensilica's TRAX-PC processor trace capture block is an optional item for use with all Tensilica Diamond Standard and Xtensa processors. It provides tracing information through an SoC's JTAG debug port without requiring added device pins. It helps designers trace all changes in program flow including exceptions and interrupts. The trace block uses a circular on-chip trace buffer with user-defined sizing to capture the trace stream and accepts PC-based triggers and external trigger inputs.

Tensilica's associated software tools convert the compressed trace into an annotated program disassembly for easy debugging. These tools are fully integrated into Tensilica's world-class Eclipse-based, Xtensa Xplorer integrated design environment (IDE). The Xplorer IDE provides a powerful visualization and debugging environment to both develop and debug programs using the TRAX-PC trace macrocell.